Internal power management scheme for a memory chip in deep power down mode
Patent 7031219 Issued on April 18, 2006. Estimated Expiration Date: 
June 4, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 4, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesFloating gate non-volatile memory with deep power down and write lock-out Static random access memory resistant to soft error Patent #: 5303190 InventorsApplicationNo. 10861157 filed on 06/04/2004US Classes:365/226, POWERING365/185.23, Drive circuitry (e.g., word line driver)365/189.11, Including level shift or pull-up circuit365/227, Conservation of power365/222, Data refresh327/540With voltage source regulatingExaminersPrimary: Elms, RichardAssistant: Nguyen, Nam Attorney, Agent or FirmInternational ClassG11C 16/06AbstractA method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode. | |
