Method for modeling integrated circuit yield
Patent 7013441 Issued on March 14, 2006. Estimated Expiration Date: 
September 26, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 26, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod for manufacturing test simulation in electronic circuit design Patent #: 5539652 InventorsApplicationNo. 10605379 filed on 09/26/2003US Classes:716/4, Testing or evaluating703/14, Circuit simulation700/121, Integrated circuit production or semiconductor fabrication716/5Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width)ExaminersPrimary: Siek, VutheAssistant: To, Tuyen Attorney, Agent or FirmInternational ClassG06F 17/50AbstractA method and system for predicting manufacturing yield for a proposed integrated circuit The method includes: in the order recited: (a) providing a multiplicity of different integrated circuit library elements in a design database, each library element linked to a corresponding normalization factor in the design database; (b) selecting library elements from the design database to include in a proposed design for the integrated circuit; (c) generating an equivalent circuit count of the proposed design based on the normalization factors and a count of each different library element included in the proposed design; and (d) calculating a predicted manufacturing yield based on the equivalent circuit count, a predicted density of manufacturing defects and an area of the proposed integrated circuit chip. | |
