Semiconductor memory device
Patent 7009881 Issued on March 7, 2006. Estimated Expiration Date: 
July 12, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 12, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesNonvolatile semiconductor member with different pass potential applied to the first two adjacent word Nonvolatile semiconductor memory device with multiple word line voltage generators Method and apparatus for reading analog values stored in floating gate nand structures Flash memory device Patent #: 6044017 InventorAssigneeApplicationNo. 10887924 filed on 07/12/2004US Classes:365/185.17, Logic connection (e.g., NAND string)365/185.03, Multiple values (e.g., analog)365/185.18, Particular biasing365/185.23, Drive circuitry (e.g., word line driver)365/185.2Reference signal (e.g., dummy cell)ExaminersPrimary: Nguyen, Tan T.Attorney, Agent or FirmForeign Patent References
International ClassG11C 16/00AbstractA semiconductor memory device includes a memory cell unit with a plurality of electrically rewritable memory cells connected in series, two ends thereof being coupled to a data transfer line and a reference potential line via select transistors, respectively, wherein the device has a data read mode defined as to detect a read current flowing between the data transfer line and the reference potential line, and judge data of a selected memory cell in the memory cell unit under the condition of: applying a read voltage to the selected memory cell, the read voltage being set to turn on or off the selected memory cell in accordance with data thereof; applying a pass voltage to remaining unselected memory cells, the pass voltage being set to turn on the remaining unselected memory cells without regard to data thereof; and making the select transistors on, and wherein in the data read mode, the more unselected memory cell or cells located on the source side of the selected memory cell, the higher the pass voltage applied to the unselected memory cell or cells located on the source side of the selected memory cell.Other References
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