Patent ReferencesMethod for performing floorplan timing analysis using multi-dimensional feedback in a spreadsheet with computed hyperlinks to physical layout graphics and integrated circuit made using same Architecture and methods for a hardware description language source level debugging system Patent #: 6132109 InventorApplicationNo. 10706228 filed on 11/12/2003US Classes:716/4, Testing or evaluating703/13, SIMULATING ELECTRONIC DEVICE OR ELECTRICAL SYSTEM714/739, Random pattern generation (includes pseudorandom pattern)714/32, Particular stimulus creation714/37Analysis (e.g., of output, state, or design)ExaminersPrimary: Siek, VutheAttorney, Agent or FirmForeign Patent References
International ClassG06F 17/50AbstractDatabase mining, analysis and optimization techniques in conjunction with the model-based functional coverage analysis are used to turn raw verification and coverage data into design intelligence (DI) and verification intelligence (VI). The required data and attributes are automatically extracted from verification, simulation and coverage analysis databases. Design finite state machine extraction, design functional event extraction, and automatic coverage model generation and optimization techniques are applied to the design HDL description. Coverage model tuning and optimization directives, as well as test spec tuning and optimization directives are generated based on the analysis and mining of various verification, simulation, and coverage databases. An integrated web-based interface portlet is used for access, analysis and management of the resulting databases, generated reports and verification directives. Dissemination rules are used to automatically generate and distribute analysis reports and verification directives to engineers at wired or wireless interface devices via Internet or Intranet. | |