Multi-level cache system with simplified miss/replacement control
Patent 7007135 Issued on February 28, 2006. Estimated Expiration Date: 
March 8, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
March 8, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSmart fill system for multiple cache network Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in a higher level cache Patent #: 6000015 InventorsAssigneeApplicationNo. 10094261 filed on 03/08/2002US Classes:711/122, Hierarchical caches711/156, Status storage711/134Combined replacement modesExaminersPrimary: Vital, Pierre M.Attorney, Agent or FirmInternational ClassG06F 12/00AbstractA multi-level cache system includes a primary cache and a secondary cache that is accessed by a processor later than the primary cache. If the secondary cache is full with data when the processor misses the access to the primary and secondary cache memories, data stored in the secondary cache must be routed to a main memory. In this case, to satisfy the inclusion property of cache, the data migrating to the main memory from the secondary cache is present in the secondary cache, not in the primary cache. The multi-level cache system does not need to access the primary cache to select the data in the secondary cache but not in the primary cache. Thus, it simplifies a logical composition for controlling the miss/replacement, and shortens an operation time therein.Other References
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