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Abstract

A low cost signature test for RF and analog circuits. A model is provided to predict one or more performance parameters characterizing a first electronic circuit produced by a manufacturing process subject to process variation from the output of one or more second electronic circuits produced by the same process in response to a selected test stimulus, and iteratively varying the test stimulus to minimize the error between the predicted performance parameters and corresponding measured values for the performance parameters, for determining an optimized test stimulus. A non-linear model is preferably constructed for relating signature test results employing the optimized test stimulus in manufacturing testing to circuit performance parameters.

Other References

• Balivada et al., “Analog Testing with Time Response Parameters”, 1996, IEEE Design & Test of Computers, pp. 18-25.
• Voorakaranam et al., “Low-Cost Signature Testing of RF Circuits”, no date on reference, pp. 2-11.
• S. J. Tsai, “Test Vector Generation for Linear Analog Devices,” International Test Conference (1991) 592-597, (No Month).
• W. Lindermeir, H.E. Graeb & K.J. Antreich, “Design of Robust Test Criteria in Analog Testing,” International Conference on Computer-Aided Design (1995) 604-611, (No Month).
• R. Voorakaranam & A. Chatterjee, “Test Generation for Accurate Prediction of Analog Specifications,” IEEE VLSI Test Symposium (2000) 137-142, (No Month).
• J.H. Friedman, “Multivariate Adaptive Regression Splines,” The Annals of Statistics, vol. 19, No. 1, 1-14L (No Date).
• P.A. Variyam and A. Chatterjee, “Specification-Driven Test Design for Analog Circuits,” International Symposium on Defect and Fault Tolerance in VLSI Systems (1998) 335-340, (No Month).
• T. Wilson, “Test Challenges for Next-Generation RF Devices,” EE Evaluation Engineering, vol. 39, No. 11 (2000) 31-37, (No Month).
• D.A. Coley, An Introduction to Genetic Algorithms for Scientists and Engineers, World Scinetific (1996) 1-16, (No Month).
• Cadence SpectreRF Simulator User Guide (Dec. 1999), 16 pages.
• Cadence OCEAN Reference Guide (Dec. 1999), 17 pages.
• RF Micro-Devices, Low Noise Amplifier/Mixer (Mar. 2001), 6 pages.
• S. Cherubal & A. Chatterjee, “Parametric Fault Diagnosis for Analog Systems Using Functional Mapping,” Proceedings, Design, Automation and Test in Europe (1999) 195-200, (No Month).
• P.N. Variyam & A. Chatterjee, “Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements,” VLSI Test Symposium (1998) 132-137, (No Month).
• A. Walker, W. Alexander & P.K. Lala, “Fault Diagnosis in Analog Circuits Using Element Modulation,” IEEE Design and Test of Computers (Mar. 1992) 19-29.
• H. Walker & S.W. Director, “VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits,” IEEE Transactions on Computer-Aided Design (Oct. 1986) 541-556.
• N.Nagi, A. Chatterjee, A. Balivada & J.A. Abraham, “Fault-Based Automatic Test Generation for Linear Analogy Devices,” Proceedings, International Conference on Computer-Aided Design (1993) 89-91, (No Month).
• M. Salamani & B. Kaminska, “Multifrequency Analysis of Faults in Analog Circuits,” IEEE Design and Test of Computers (1995) 70-80, (No Month).
• B. Hamida, K. Saab, D. Marche, B. Kaminska & G. Qusnel, “LIMSoft: Automated Tool for Design and Test Integration of Analog Circuits,” International Test Conference (1996) 571-580, (No Month).
• H.H. Zheng, A. Balivada & J.A. Abraham, “A Novel Test Generation Approach for Parametric Faults in Linear Analog Circuits,” VLSI Test Symposium (1996) 470-475, (No Month).
• A. Abderrahman, E. Cerny & B. Kaminska, “CLP-Based Multifrequency Test Generation for Analog Circuits,” VLSI Test Symposium (1997) 158-165, (No Month).
• G. Devarayanadurg & M. Soma, “Dynamic Test Signal Design for Analog ICs,” Proceedings, International Conference on Computer-Aided Design (1995) 627-629, (no month).
• W. Verhaegen, G. Van de Plas & G. Gielen, “Automated Test Pattern Generation for Analog ICs,” Proceedings, VLSI Test Symposium (1997) 296-301, (no month).
• J.B. Brockman & S.W. Director, “Predictive Subset Testing: Optimizing IC Parametric Performance Testing for Quality, Cost and Yield,” IEEE Transactions on Semiconductor Manufacturing, vol. 2 (1989) 104-113, (no month).
• W. Maly & Z. Pizlo, “Tolerance Assignment for IC Selection Tests,” IEEE Transactions on Computer-Aided Design (Apr. 1985) 156-162.
• T.M. Souders & G.N. Stenbakken, “Cutting the High Cost of Testing,” IEEE Spectrum (Mar. 1991) 48-51.
• S.D. Huss & R.S. Gyurcsik, “Optimal Ordering of Analog IC Tests to Minimize Time,” Proceedings, Design Automation Conference (1991) 494-499, (no month).
• L. Milor & A.L. Sangiovanni-Vincentelli, “Minimizing Production Test Time to Detect Faults in Analog Circuits,” IEEE Transactions on Computer-Aided Design, vol. 13 (1994) 796-813, (no month).
• M.J. Marlett & J.A. Abraham, “DC-JATP: An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests,” Proceedings, IEEE International Test Conference (1988) 839-845, (no month).
• G. Devarayanadurg & M. Soma, “Analytic Fault Modeling and Static Test Generation for Analog ICs,” International Conference for Computer-Aided Design (1994) 44-47, (no month).
• W.M. Lindermeir, H.E. Graeb & K.J. Antreich, “Design Based Analog Testing by Characteristic Observation Inference,” International Conference for Computer-Aided Design (1995) 620-626, (no month).
• C.Y. Pan & K.T. Cheng, “Implicit Functional Testing for Analog Circuits,” VLSI Test Symposium (1996) 489-494, (no month).
• P.N. Variyam & A. Chatterjee, “Test Generation for Comprehensive Testing of Linear Analog Circuits Using Transient Response Sampling”, International Conference on Computer-Aided Design (1997) 382-385, (no month).
• K.J. Antreich, H.E. Graeb & C.U. Wieser, “Circuit Analysis and Optimization Driven by Worst Case Distances,” IEEE Transaction on CAD, vol. 13 (1994) 57-71, (no month).
• D.G. Saab, Y.G. Saab & J.A. Abraham, “CRIS: A Test Cultivation Program for Sequential VLSI Circuits,” Proceedings: International Conference on Computer-Aided Design (1992) 216-219, (no month).
• G. Devarayanadurg, P. Goteti & M. Soma, “Hierarchy Based Statistical Fault Simulation of Mixed-Signal ICs,” International Test Conference (1996) 521-527, (nno month).
• A. Basilevsky, “Statistical Factor Analysis and Related Methods, Theory and Applications,” Wiley Series in Probability and Mathematics (1994), 44 pages, (no month).
• I.T. Joliffe, “Discarding Variables in a Principle Component Analysis, I. Artificial Data,” Applied Statistics, vol. 22 (1973) 21-31, (No Month).
• L. Milor & A. L. Sangiovanni-Vincentelli, “Optimal Test Set Design for Analog Circuits,” International Conference on Computer-Aided Design (1990) 294-297, (No Month).
• A.V. Gomes & A. Chatterjee, “Minimal Length Diagnostic Tests for Analog Circuits Using Test History,” Design, Automation and Test in Europe (1999) 189-194, (No Month).
• MATLAB 0ptimization Toolbox User's Guide, 4 pages, (No Date).