U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Digital background cancellation of digital to analog converter mismatch noise in analog to digital converters

Patent 7006028 Issued on February 28, 2006. Estimated Expiration Date: Icon_subject May 11, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

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Issued on: 09/28/1993
Inventor: Babu, et al.

Multi-bit oversampled DAC with dynamic element matching
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Inventor: Leung

Multi-stage A/D converter
Patent #: 5436629
Issued on: 07/25/1995
Inventor: Mangelsdorf

Processor controlled analog-to-digital converter circuit
Patent #: 5892472
Issued on: 04/06/1999
Inventor: Shu, et al.

Multi-stage delta sigma modulator with one or more high order sections
Patent #: 5949361
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Inventor

Application

No. 10844047 filed on 05/11/2004

US Classes:

341/155, Analog to digital conversion341/156, Coarse and fine conversions341/144, Digital to analog conversion341/150, Using charge coupled devices or switched capacitances341/161Acting sequentially

Examiners

Primary: Nguyen, Dinh Q.

Attorney, Agent or Firm

International Class

H03M 1/12

Abstract

Devices for performing analog-to-digital conversion with reduced noise. In one implementation, an analog-to-digital converter includes at least one internal digital-to-analog converter (DAC) that comprises a plurality of analog components and converts an intermediate digital signal into an associated intermediate analog signal, a dynamic element matching (DEM) circuit coupled to the DAC to permute configurations of the analog components within the DAC, a noise cancellation circuit and a digital subtractor block. The noise cancellation circuit is coupled to receive a first digital sequence comprising a component of a digitized representation of an analog output of the DAC, and a second digital sequence representing a state of the DEM circuitry. The noise cancellation circuit is operable to combine the first and the second digital sequences so as to estimate a digital representation of a DAC noise caused by error sequence introduced mismatches among the analog components within the DAC. The digital subtractor block is coupled to the noise cancellation circuit and operable to use the estimated digital representation of the DAC noise to reduce the DAC noise.

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