U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Single or multi-layer printed circuit board with recessed or extended breakaway tabs and method of manufacture thereof

Patent 7002081 Issued on February 21, 2006. Estimated Expiration Date: Icon_subject August 3, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3451793

3469982

3663389

3738835

3749657

3793278

3833436

3928157

Method of fabricating metal printed wiring boards
Patent #: 3934334
Issued on: 01/27/1976
Inventor: Hanni

Method of electrodepositing self-crosslinking cationic compositions
Patent #: 3947338
Issued on: 03/30/1976
Inventor: Jerabek ,   et al.

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Inventors

Assignee

Application

No. 10910022 filed on 08/03/2004

US Classes:

174/260, With electrical device174/255, With particular substrate or support structure174/262, Feedthrough257/783, With adhesive means257/674, With means for controlling lead tension361/760, Connection of components to board361/826Wire distribution (e.g., harness, rack, etc.)

Examiners

Primary: Cuneo, Kamand
Assistant: Patel, Ishwar (I. B.)

Attorney, Agent or Firm

Foreign Patent References

  • 2707405 DE 01/01/1978
  • 0012463 EP 06/01/1982
  • 0264105 EP 10/01/1987
  • 0272500 EP 06/01/1988
  • 0365755 EP 07/01/1989
  • 0523479 EP 07/01/1992
  • 0573053 EP 12/01/1993
  • 2041471 FR 01/01/1971
  • 0264105 GB 04/01/1988
  • 59133232 JP 07/01/1984
  • 02241089 JP 03/01/1989
  • 02087590 JP 03/01/1990
  • 04071285 JP 07/01/1990
  • 5320313 JP 12/01/1993
  • 06268378 JP 09/01/1994
  • 08288660 JP 04/01/1995
  • 11071501 JP 08/01/1997
  • 11021359 JP 01/01/1999
  • 11145205 JP 05/01/1999
  • 2001305750 JP 11/01/2001
  • WO 98/20559 WO 05/01/1998
  • WO01/77753 WO 10/01/2001

International Class

H05K 1/16

Abstract

A circuit board layer 2 in accordance with the present invention includes a conductive sheet 4 sandwiched between an insulating top layer 10 and an insulating bottom layer 14. The top and bottom layers 10 and 14 and the conductive sheet 4 define the circuit board layer 2 having an edge that includes an edge 20 of the conductive sheet 4. An insulating edge layer 18 covers substantially all of the edge 20 of the conductive sheet 4.

Other References

  • PARYLENE; A Protective Conformal Coating for Hybrid Circuits, Speedline Technologies (2000).
  • SCS Parylene Specifications and Properties product literature, Speedlino Technologies (2000).
  • Encyclopedia of Chemical Technology, Fourth Edition, Supplement Volume, p. 863-901 (1998).
  • IPC-TM-650 Test Methods Manual, No. 2.3.10, Flammability of Laminates Dec. 1994, pp. 1-3.
  • Polymers for Microelectronics, Presented at the 203rd National Meeting of American Chemical Society, Apr., 1992, Chapter 353. pp. 507-508, by Larry F. Thompson et al.
  • Handbook of Flixible Circuits, p. 242, 1991 by Ken Gilleo.
  • Handbook of Polymer Coatings for Electronics, pp. 114-118, 2nd Edition, by James J. Licari, et al.
  • “Decoupling Capacitor Attachment Method,” Research Disclosure, Kenneth Mason. Publications, Hampshire, GB, No. 319, Nov. 1990, p. 880.
  • “Printed wiring boards incorporating Cu-invar-Cu layers,” 8028 Electronic Components & Applications, Alfred Goberecht, vol. 10 No. 1, pp. 12-16.
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