System and method for generating a two-dimensional yield map for a full layout

Patent 6996790 Issued on February 7, 2006. Estimated Expiration Date:

January 30, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Inventor

Chang, Fang-Cheng

Application

No. 10354382 filed on 01/30/2003

US Classes:

716/4, Testing or evaluating716/19, DESIGN OF SEMICONDUCTOR MASK716/21, Pattern exposure703/13, SIMULATING ELECTRONIC DEVICE OR ELECTRICAL SYSTEM382/145, Inspection of semiconductor device or printed circuit board700/110, Defect analysis or recognition716/8Floorplanning

Examiners

Primary: Garbowski, Leigh Marie

Attorney, Agent or Firm

Kenta Suzue Haynes Beffel & Wolfeld LLP

Foreign Patent References

0 910 123 EP 04/01/1999

International Classes

G06F 17/50
G06K 9/00

Abstract

A two-dimensional yield map for a device, such as an integrated circuit, in a fabrication facility is computed and associated with layout data for the device in a hierarchical and/or instance-based layout file. The device has a layout including a pattern characterizable by a combination of members of a set of basis shapes. A set of basis pre-images include yield map data representing an interaction of respective members of the set of basis shapes with a defect model. A yield map for the pattern is created by combining basis pre-images corresponding to basis shapes in the combination of members that characterize the pattern to provide a combination result. The output may be displayed as a two dimensional map to an engineer performing yield analysis, or otherwise processed.

Other References

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Pati, Y.C., et al., “Explointing Structure in Fast Aerial Image Computation for Integrated Circuit Patterns,” IEEE Transactions on Semiconductor Manufacturing, vol. 10, No. 1 (Feb. 1997) 62-73.