Rail stack array of charge storage devices and method of making same

Patent 6992349 Issued on January 31, 2006. Estimated Expiration Date:

May 20, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Inventors

Assignee

Matrix Semiconductor, Inc.

Application

No. 10849000 filed on 05/20/2004

US Classes:

257/324, Multiple insulator layers (e.g., MNOS structure)438/261, Multiple interelectrode dielectrics or nonsilicon compound gate insulator365/185.05Particular connection

Examiners

Primary: Weiss, Howard

Attorney, Agent or Firm

Foley & Lardner LLP

Foreign Patent References

0 073 486 EP 08/01/1982
0 387 834 EP 09/01/1990
0387834 EP 09/01/1990
0 395 886 EP 11/01/1990
0 516 866 EP 12/01/1992
0 606 653 EP 07/01/1994
0 644 548 EP 09/01/1994
0 800 137 EP 03/01/1997
1017 100 EP 07/01/2000
61-222216 JP 10/01/1986
5-082787 JP 04/01/1993
6-22352 JP 01/01/1994
6-338602 JP 12/01/1994
63-52463 JP 03/01/1998
WO 94/26083 WO 11/01/1994

International Classes

H01L 29/792
H01L 21/336

Abstract

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Other References

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