Soi annealing method for reducing HF defects, with lamp, without crystal original particle (COP)
Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device
Shallow photonic bandgap device
Method of manufacturing semiconductor device for evaluation capable of evaluating crystal defect using in-line test by avoiding using preferential etching process
Integrated photodevice and waveguide Patent #: 6813431
ApplicationNo. 10828898 filed on 04/21/2004
US Classes:385/131, Multilayer structure (mixture)257/431, Light385/125, Utilizing nonsolid core or cladding385/129PLANAR OPTICAL WAVEGUIDE
ExaminersPrimary: Wille, Douglas A.
AbstractA conventional CMOS fabrication technique is used to integrate the formation of passive optical devices and active electro-optic devices with standard CMOS electrical devices on a common SOI structure. The electrical devices and optical devices share the same surface SOI layer (a relatively thin, single crystal silicon layer), with various required semiconductor layers then formed over the SOI layer. In some instances, a set of process steps may be used to simultaneously form regions in both electrical and optical devices. Advantageously, the same metallization process is used to provide electrical connections to the electrical devices and the active electro-optic devices.