Discriminative SOI with oxide holes underneath DC source/drain
January 8, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesStacked MOS device with means to prevent substrate floating Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing Method for making patterned implanted buried oxide transistors and structures Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode Semiconductor-on-insulator electronic devices having trench isolated monocrystalline active regions Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility MOSFET on SOI substrate Latex prophylactics SOI (silicon on insulator) device and method for fabricating the same Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate InventorApplicationNo. 10754320 filed on 01/08/2004US Classes:257/347, Single crystal semiconductor layer on insulating substrate (SOI)257/349, With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate257/351, Complementary field effect transistor structures only (i.e., not including bipolar transistors, resistors, or other components)257/352, Substrate is single crystal insulator (e.g., sapphire or spinel)257/507, With single crystal insulating substrate (e.g., sapphire)128/842, MALE REPRODUCTORY TRACT SHIELDS OR BIRTH CONTROL DEVICES (E.G., PROPHYLACTICS, VAS DEFERENS VALVES, ETC.)438/164Semiconductor islands formed upon insulating substrate or layer (e.g., mesa formation, etc.)ExaminersPrimary: Huynh, AndyAttorney, Agent or FirmForeign Patent References
International ClassH01L027/01AbstractA selective SOI structure having body contacts for all the devices while excluding the buried oxide that is directly underneath diffusions of DC nodes such as applied voltage Vdd, ground GND, reference voltage Vref, and other like DC nodes is provided. The selective SOI structure of the present invention can be used in ICs to enhance the performance of the circuit. The selective SOI structure of the present invention includes a silicon-on-insulator (SOI) substrate material comprising a top Si-containing layer having a plurality of SOI devices located thereon. The SOI devices are in contact with an underlying Si-containing substrate via a body contact region. A DC node diffusion region not containing an underlying buried oxide region is adjacent to one of the SOI devices.Field of SearchDepletion mode field effect transistorSingle crystal islands of semiconductor layer containing only one active device Substrate is single crystal insulator (e.g., sapphire or spinel) Including means to eliminate island edge effects (e.g., insulating filling between islands, or ions in island edges) Insulated electrode device is combined with diverse type device (e.g., complementary MOSFETs, FET with resistor, etc.) Single crystal semiconductor layer on insulating substrate (SOI) With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate Complementary field effect transistor structures only (i.e., not including bipolar transistors, resistors, or other components) With single crystal insulating substrate (e.g., sapphire) | |
