Data transfer control circuit with terminal sharing
Patent 6944686 Issued on September 13, 2005. Estimated Expiration Date: 
September 26, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 26, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesApparatus and method for cooperative and concurrent coprocessing of digital information DMA controller arrangement having plurality of DMA controllers and buffer pool having plurality of buffers accessible to each of the channels of the controllers Method and apparatus for placing multiple frames of data in a buffer in a direct memory access transfer Efficient data transfer mechanism for input/output devices Patent #: 6049842 InventorsAssigneeApplicationNo. 10255024 filed on 09/26/2002US Classes:710/39, Access request queuing710/19, Status updating710/305, Bus interface architecture710/112, Bus request queuing710/22, Direct Memory Accessing (DMA)710/33Data transfer specifyingExaminersPrimary: Park, IlwooAttorney, Agent or FirmInternational ClassG06F013/28AbstractA DMA controller including a request queue for holding DMA transfer requests clears only the request queue without executing unnecessary DMA transfers and provides information about the states of the queue. A DMA controller is configured to enable data transfer control with respect to plural channels and includes a request queue capable of holding the identification information of channels concerned in plural data transfer requests, wherein the states of the request queue can be outputted and information held in the request queue can be cleared. | |
