Methods for reducing bitline voltage offsets in memory devices
December 17, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor memory cell margin test circuit Bipolar static semiconductor memory device with a high cell holding margin High speed eprom cell and array Seven transistor content addressable memory (CAM) cell Bit line and column circuitry used in a semiconductor memory High speed zero power reset circuit for CMOS memory cells Self restoring ferroelectric memory Resetting arrangement for a semiconductor integrated circuit device having semiconductor memory Semiconductor memory device with bit line pairs crossed at least once with respect to each other Semiconductor storage device with common data line structure InventorAssigneeApplicationNo. 10026246 filed on 12/17/2001US Classes:703/14, Circuit simulation703/13, SIMULATING ELECTRONIC DEVICE OR ELECTRICAL SYSTEM703/15, Including logic716/17, Programmable integrated circuit (e.g., basic cell, standard cell, macrocell)365/233, Sync/clocking365/207, Differential sensing365/222, Data refresh365/201, Testing365/190, For complementary information365/49, ASSOCIATIVE MEMORIES365/156, Complementary365/145, Ferroelectric365/51, FORMAT OR DISPOSITION OF ELEMENTS365/154, Flip-flop (electrical)365/205, Flip-flop used for sensing365/182, Insulated gate devices365/230.05, Multiple port access365/202, Complementing/balancing365/63, INTERCONNECTION ARRANGEMENTS365/189.05, Having particular data buffer or latch365/203, Precharge365/189.11, Including level shift or pull-up circuit365/189.09, Including reference or bias voltage generator365/200, Bad bit257/776, Cross-over arrangement, component or structure365/189.01, READ/WRITE CIRCUIT365/185.21, Sensing circuitry (e.g., current mirror)365/150, Inherent365/149, Capacitors257/390, Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM))365/185.3, Over erasure365/221, Serial read/write365/191, Signals365/185.2, Reference signal (e.g., dummy cell)365/210Reference or dummy elementExaminersPrimary: Homere, Jean R.Assistant: Ferris, Fred Attorney, Agent or FirmForeign Patent References
International ClassesG06F017/50G11C011/34 G11C011/34 G11C011/401 G11C011/401 G11C011/41 G11C011/401 AbstractA method of designing a memory device that has substantially reduced bitline voltage offsets is provided. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a core cell having a bitline and a complementary bitline, and designing a flipped core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a core cell followed by a flipped core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the core cell is coupled with the flipped complementary bitline of the flipped core cell, and the complementary bitline of the core cell is coupled to the flipped bitline of the flipped core cell.Other References
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