Three-dimensional integrated semiconductor devices
September 30, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcess for producing a three-dimensional semiconductor device Stacked semiconductor device Multi-layer type semiconductor device with semiconductor element layers stacked in opposite direction and manufacturing method thereof Method of making a three-dimensional integrated circuit Ultra high density inverter using a stacked transistor arrangement Elevated transistor fabrication technique Patent #: 6420730 InventorAssigneeApplicationNo. 10260840 filed on 09/30/2002US Classes:438/152, Combined with electrical device not on insulating substrate or layer438/18, Utilizing integral test element257/353, Single crystal islands of semiconductor layer containing only one active device257/74, Plural recrystallized semiconductor layers (e.g., "3-dimensional integrated circuit")257/327, Short channel insulated gate field effect transistor257/67In combination with device formed in single crystal semiconductor material (e.g., stacked FETs)ExaminersPrimary: Nelms, David C.Assistant: Hoang, Quoc Attorney, Agent or FirmForeign Patent References
International ClassH01L021/00AbstractThe present invention describes a process for three-dimensional integration of semiconductor devices and a resulting device. The process combines low temperature wafer bonding methods with backside/substrate contact processing methods, preferably with silicon on insulator devices. The present invention utilizes, in an inventive fashion, low temperature bonding processes used for bonded silicon on insulator (SOI) wafer technology. This low temperature bonding technology is adopted for stacking several silicon layers on top of each other and building active transistors and other circuit elements in each one. The back-side/substrate contact processing methods allow the interconnection of the bonded SOI layers.Other References
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