U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Integrated back-end integrated circuit manufacturing assembly

Patent 6931298 Issued on August 16, 2005. Estimated Expiration Date: Icon_subject February 27, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Manipulation and handling of integrated circuit dice
Patent #: 4915565
Issued on: 04/10/1990
Inventor: Bond, et al.

Method of manufacturing an enclosed transceiver
Patent #: 6045652
Issued on: 04/04/2000
Inventor: Tuttle, et al.

Apparatus for removing contaminants on electronic devices
Patent #: 6230719
Issued on: 05/15/2001
Inventor: Wensel

Semiconductor chip packaging system and a semiconductor chip packaging method using the same
Patent #: 6392286
Issued on: 05/21/2002
Inventor: Jin, et al.

Stereolithographic method and apparatus for packaging electronic components and resulting structures
Patent #: 6549821
Issued on: 04/15/2003
Inventor: Farnworth, et al.

Method and system for universal packaging in conjunction with a back-end integrated circuit manufacturing process
Patent #: 6730532
Issued on: 05/04/2004
Inventor: Chang, et al.

Method of performing back-end manufacturing of an integrated circuit device Patent #: 6730545
Issued on: 05/04/2004
Inventor: Chang, et al.

Inventor

Assignee

Application

No. 10085757 filed on 02/27/2002

US Classes:

700/121, Integrated circuit production or semiconductor fabrication438/106, PACKAGING (E.G., WITH MOUNTING, ENCAPSULATING, ETC.) OR TREATMENT OF PACKAGED SEMICONDUCTOR29/740, Chip component156/292, Of laminae having opposed facing areas out of contact134/1.1, Plasma cleaning257/660, With means to shield device contained in housing or package from charged particles (e.g., alpha particles) or highly ionizing radiation (i.e., hard X-rays or shorter wavelength)700/120, Stereolithography438/25, Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor438/112And encapsulating

Examiners

Primary: Picard, Leo P.
Assistant: Jarrett, Ryan

Attorney, Agent or Firm

International Classes

G06F019/00
H01L021/44
H01L021/48
H01L021/50

Abstract

An integrated back-end integrated circuit (IC) manufacturing assembly is disclosed. In one embodiment, the present invention has a front-of-line portion comprising a plurality of integrated sub-stations for operating on a first plurality of die-strips on an in-line basis to produce a second plurality of die-strips. The present embodiment further comprises an end-of-line portion coupled to the front-of-line portion and comprising a plurality of integrated sub-stations for operating on the second plurality of die-strips on an in-line basis to produce die-strip components. The present embodiment also comprises an in-line test portion coupled to the end-of-line portion for testing the die-strip components. The present embodiment further comprises a finish portion coupled to the in-line test portion and comprising a plurality of integrated sub-stations operating on tested die-strip components. In addition, camera systems perform automated visual inspection of dies on the die-strip and maintain a database that can be used for automated reject management.

Other References

  • T. Olson, “Emerging Package-less Strip Designs Demand Innovative Manufacturing Approaches”, Semiconductor Magazine, vol. 1, Isuue 4, Apr. 2000, P58, 2 Sheets.
  • L. Estacio, “Cypress Semiconductor Leads the Way with Advance Strip Level Tracking”, Semiconductor Magazine, vol. 1, Issue 4, Apr. 2000, P60, 1 Sheet.
  • J. Pedro, L. Estacio, “Using Electronic Strip Mapping for Tracking Defects in a Fully Integrated Assembly and Test Line”, 8 Sheets.
  • C.T. Choon, K.R. Vadivazhagu, N.H. Sieng, :Automation/Integration Program in TAP Reality Vs Vision, Test Assembly & Packaging 1999, 8 Sheets.
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