Semiconductor process yield analysis based on evaluation of parametric relationship

Patent 6885955 Issued on April 26, 2005. Estimated Expiration Date:

March 28, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Method for analyzing probe yield sensitivities to IC design
Patent #: 6210983
Issued on: 04/03/2001
Inventor: Atchison, et al.

Method for the calculation of wafer probe yield limits from in-line defect monitor data
Patent #: 6324481
Issued on: 11/27/2001
Inventor: Atchison, et al.

Method of a comprehensive sequential analysis of the yield losses of semiconductor wafers Patent #: 6393602
Issued on: 05/21/2002
Inventor: Atchison, et al.

Inventor

Atchison, Nickey Joe

Assignee

Cypress Semiconductor Corp.

Application

No. 10402774 filed on 03/28/2003

US Classes:

702/81, Quality evaluation702/85, CALIBRATION OR CORRECTION SYSTEM438/14WITH MEASURING OR TESTING

Examiners

Primary: Barlow, John
Assistant: Walling, Meagan S

Attorney, Agent or Firm

Graham; David R.

International Classes

G01N037/00
G01D018/00
G01R031/26

Abstract

Semiconductor process yield analysis in which the relationship between a wafer-level parameter and a die-level parameter is evaluated can be performed more quickly and with greater accuracy than has been the case with previous such yield analysis. The yield analysis can be performed by selecting regions of a semiconductor wafer or wafers from which parametric data is to be obtained for use in the analysis, based on one or more characteristics of the wafer(s). The yield analysis can be performed by grouping the parametric data based on both a grouping of the wafer-level parametric data and a grouping of the die-level parametric data. The yield analysis can be performed by grouping the parametric data in greater than 3 groups.