Test circuit and multi-chip package type semiconductor device having the test circuit
Patent 6885095 Issued on April 26, 2005. Estimated Expiration Date: 
December 30, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 30, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMass memory and method for the manufacture of mass memories Boundary-scan method using object-oriented programming language LSI device with memory and logics mounted thereon Merged memory and logic (MML) integrated circuits including memory test controlling circuits and methods Patent #: 6216240 InventorsAssigneeApplicationNo. 10747230 filed on 12/30/2003US Classes:257/686, Stacked arrangement257/48, TEST OR CALIBRATION STRUCTURE257/693, External connection to housing324/713With voltage or current signal evaluationExaminersPrimary: Flynn, Nathan J.Assistant: Andujar, Leonardo Attorney, Agent or FirmForeign Patent References
International ClassesH01L023/02G01R031/28 H01L021/66 G01R031/28 AbstractA MCP semiconductor device includes at least first and second chips, each of which has internal pads and an internal circuit, encapsulated by a sealing material together. The device further includes a test circuit. The test circuit connects each of the internal pads to one of the internal circuits under a normal operation mode of the device, and disconnect between them under a test mode. | |
