Mass memory and method for the manufacture of mass memories
Boundary-scan method using object-oriented programming language
LSI device with memory and logics mounted thereon
Merged memory and logic (MML) integrated circuits including memory test controlling circuits and methods Patent #: 6216240
ApplicationNo. 10747230 filed on 12/30/2003
US Classes:257/686, Stacked arrangement257/48, TEST OR CALIBRATION STRUCTURE257/693, External connection to housing324/713With voltage or current signal evaluation
ExaminersPrimary: Flynn, Nathan J.
Assistant: Andujar, Leonardo
Attorney, Agent or Firm
Foreign Patent References
AbstractA MCP semiconductor device includes at least first and second chips, each of which has internal pads and an internal circuit, encapsulated by a sealing material together. The device further includes a test circuit. The test circuit connects each of the internal pads to one of the internal circuits under a normal operation mode of the device, and disconnect between them under a test mode.