Method for evaluation of scalable symmetric multiple processor cache coherency protocols and algorithms
Patent 6883071 Issued on April 19, 2005. Estimated Expiration Date: 
May 10, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
May 10, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMultiprocessor arrangement including bus arbitration scheme involving plural CPU clusters that address each other as "phantom" CPUs Apparatus and method for computer system interrupt emulation Method and system for low level testing of central electronics complex hardware using Test nano Kernel Patent #: 6357020 InventorsAssigneeApplicationNo. 10841555 filed on 05/10/2004US Classes:711/141, Coherency711/171, Based on data size711/119, Multiple caches711/172, Based on component size703/28In-circuit emulator (i.e., ICE)ExaminersPrimary: Sparks, DonaldAssistant: Peugh, Brian R. International ClassG06F012/00AbstractA system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.Other References
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