EEPROM architecture and programming protocol
December 15, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesNon-volatile semiconductor memory device incorporating data latch and address counter for page mode programming Non-volatile semiconductor memory device incorporating data latch and address counter for page mode programming Semiconductor memory device having a plurality of I/O terminal groups Non-volatile semiconductor memory device having large margin of readout operation for variation in external power supply voltage Flash memory architecture that utilizes a time-shared address bus scheme and separate memory cell access paths for simultaneous read/write operations Random access memory having burst mode capability and method for operating the same Microcontroller including a single memory module having a data memory sector and a code memory sector and supporting simultaneous read/write access to both sectors Semiconductor memory device and regulator Semiconductor device that enables simultaneous read and write/erase operation Nonvolatile memory, IC card and data processing system Patent #: 6687164 InventorsAssigneeApplicationNo. 10737676 filed on 12/15/2003US Classes:365/185.05, Particular connection365/185.23, Drive circuitry (e.g., word line driver)365/185.25, Line charging (e.g., precharge, discharge, refresh)365/185.12, Parallel row lines (e.g., page mode)365/185.21, Sensing circuitry (e.g., current mirror)365/185.11, Bank or block architecture365/230.08, Including particular address buffer or latch circuit arrangement712/37, Programmable (e.g., EPROM)365/189.05, Having particular data buffer or latch365/185.13, Global word or bit lines365/185.29EraseExaminersPrimary: Phan, TrongAttorney, Agent or FirmInternational ClassesG11C016/04G11C016/06 AbstractAn EEPROM memory circuit in which the loading of the column latches can be performed simultaneously with reading of the memory array. In this memory circuit, the data input connects directly to the column latches, leaving the bit lines open for memory reading by the sense amplifiers, which is connected directly to the bit lines. Two separate Y address decoders, one feeding into the column latches and the other into the bit line select circuit, provide column latch and bit line selection respectively. | |
