Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus
Deskew circuit in a host interface circuit
Peripheral buses for integrated circuit
Virtual component on-chip interface
Method and system for optimizing data transfers between devices interconnected by buses operating at different clocking speeds Patent #: 6633994
ApplicationNo. 10022380 filed on 11/30/2001
US Classes:710/300, Bus expansion or extension713/320, Power conservation713/401, Using delay713/501, Multiple or variable intervals or frequencies710/311, Intelligent bridge710/315, Different protocol (e.g., PCI to ISA)365/233, Sync/clocking710/305, Bus interface architecture713/600CLOCK CONTROL OF DATA PROCESSING SYSTEM, COMPONENT, OR DATA TRANSMISSION
ExaminersPrimary: Lee, Thomas C.
Assistant: Amin, Nirav
Attorney, Agent or Firm
AbstractSystem (50), e.g. a System on a chip (SoC), comprising a system bus (56), a high-speed functional block (51) operably linked to the system bus (56), and a high-speed clock line (54) for applying a high-speed clock to the high-speed functional block (51). The system (50) further comprises a peripheral bus (59), a low-speed functional block (52) operably linked to this peripheral bus (59), a circuitry (53) for generating a wait signal (PWAIT), a low-speed clock line (57) for applying a low-speed clock (PCLK) to the low-speed functional block (52), a select line (58) for feeding a select signal (PSEL) from the peripheral bus (59) to the low-speed functional block (52), an enable line (55) for applying a clock enable signal (PCLKEN) to the circuitry (53), and a wait line (61) for feeding the wait signal (PWAIT) to the high-speed functional block (51). The circuitry (53) generates the wait signal (PWAIT) from the select line signal (PSEL) and the clock enable signal (PCLKEN).