Nonvolatile semiconductor memory device with first and second read modes
Patent 6842377 Issued on January 11, 2005. Estimated Expiration Date: 
April 11, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 11, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor memory device with switchable sense amps Semiconductor memory device Semiconductor memory device Method and apparatus for a nonvolatile memory interface for burst read operations Read-ahead electrically erasable and programmable serial memory Nonvolatile semiconductor memory having page mode with a plurality of banks Patent #: 6671203 InventorsAssigneeApplicationNo. 10412646 filed on 04/11/2003US Classes:365/185.21, Sensing circuitry (e.g., current mirror)365/185.33, Flash365/189.02, Multiplexing365/238.5, Byte or page addressing710/35, Burst data transfer365/221, Serial read/write365/185.11, Bank or block architecture365/200Bad bitExaminersPrimary: Mai, SonAttorney, Agent or FirmForeign Patent References
International ClassesG11C 1606G11C 1606 AbstractA nonvolatile semiconductor memory device with a plurality of read modes switchably built therein is provided. This nonvolatile semiconductor memory device is the one that has a memory cell array in which electrically rewritable nonvolatile memory cells are laid out and a read circuit which performs data readout of the memory cell array. The nonvolatile semiconductor memory device has a first read mode and a second read mode. The first read mode is for reading data by means of parallel data transfer of the same bit number when sending data from the memory cell array through the read circuit up to more than one external terminal. The second read mode is for performing parallel data transfer of a greater bit number than that of the first read mode when sending data from the memory cell array to the read circuit while performing data transfer of a smaller bit number than the bit number when sending data from the read circuit up to the external terminal. | |
