PLD configurable logic block enabling the rapid calculation of sum-of-products functions
August 30, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod for implementing large multiplexers with FPGA lookup tables FPGA configurable logic block with multi-purpose logic/memory circuit Method for implementing large multiplexers with FPGA lookup tables System and method for comparing values during logic analysis Configurable logic element with expander structures Configurable lookup table for programmable logic devices Patent #: 6400180 InventorsApplicationNo. 10233244 filed on 08/30/2002US Classes:326/41, Significant integrated structure, layout, or layout interconnections326/47, Significant integrated structure, layout, or layout interconnections326/38, Having details of setting or programming of interconnections or logic functions340/146.2DIGITAL COMPARATOR SYSTEMSExaminersPrimary: Tan, VibolAttorney, Agent or FirmInternational ClassH03K 19177AbstractA variety of CLB architectures enable the efficient implementation of sum-of-products functions in a PLD. Output signals from each lookup table (LUT) in a CLB are routed directly to a dedicated OR structure, bypassing other logic typically included in a CLB. Thus, the LUTs can be programmed to implement AND functions, with the AND function results being ORed together in the dedicated OR structure. In this manner, a fast and efficient sum-of-products output signal is provided. In some embodiments, the dedicated OR structure includes programmable means for selectively combining the signals from the LUTs. In these embodiments, LUTs with output signals that are ignored by the dedicated OR structure can be used to implement unrelated logic.Other References
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