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US Patent 6829670 - Using consecutive block IDs to keep track of data transferred across a serially linked bridge
US Patent Issued on December 7, 2004
Estimated Patent Expiration Date:
November 1, 2020Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
November 1, 2020Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA PCI-PCI bridge is composed of two physically different controllers, i.e., a primary PCI serial transfer controller arranged at a PC, and a secondary PCI serial transfer controller arranged at a docking station. In data transfer between these controllers, preliminary transmission of block data having a block ID assigned thereto and a return of ACK having the block ID assigned thereto are performed asynchronously. The transmission party can determine which data item is the last the receiving party has received by employing a block ID assigned to NAK. When NAK is received from the receiving party, re-transmission from a block waiting for NAK is started. In this manner, data required to transmit a bus transaction between buses can be transferred accurately and speedily between two controllers. | InventorApplicationNo. 09702755 filed on 11/01/2000US Classes:710/310, Buffer or que control370/235, Flow control of data transmission through a network370/394, Sequencing or resequencing of packets to insure proper output sequence order714/748Request for retransmissionField of Search710/309, Arbitration710/311, Intelligent bridge710/312, Multiple bridges710/310, Buffer or que control710/313, Peripheral bus coupling (e.g., PCI, USB, ISA, and etc.)710/307, Variable or multiple bus width710/314, Common protocol (e.g., PCI to PCI)710/308, Direct memory access (e.g., DMA)710/306, Bus bridge710/305, Bus interface architecture710/315, Different protocol (e.g., PCI to ISA)370/235.1, Using leaky bucket technique370/251, Having dedicated test line or channel370/247, Having a dedicated test line or channel370/240, In a star coupler370/239, Using antijabber circuit370/249, Loopback370/234, Measurement of the average data flow rate370/246, Of a repeater370/238.1, ATM least cost routing370/225, Bypass an inoperative channel370/248, Path check370/241.1, Using OAM (Operation, Administration and Maintenance) cells370/233, Measurement of the peak data flow rate370/236.2, Using OAM (Operation, Administration and Maintenance) cells370/245, Of a local area network370/250, Of a switching system370/243, Of a repeater system370/253, Measurement of flow rate of messages having an address header370/244, Of a switching system370/229, DATA FLOW CONGESTION PREVENTION OR CONTROL370/236.1, Using RM (Resource Management) cells370/242, Fault detection370/226, In a repeater system370/228, Spare channel370/227, Using a spare channel370/224, Loopback of signals on the secondary ring or loop370/238, Least cost or minimum delay routing370/235, Flow control of data transmission through a network370/237, Congestion based rerouting370/252, Determination of communication parameters370/241, DIAGNOSTIC TESTING (OTHER THAN SYNCHRONIZATION)370/231, End-to-end flow control370/232, Based on data flow rate measurement370/236, Including signaling between network elements370/230.1, Traffic shaping370/230, Control of data admission to the network370/394, Sequencing or resequencing of packets to insure proper output sequence order370/473, Transmission of a single message having multiple packets709/237, Computer-to-computer handshaking709/233, Transfer speed regulating709/234, Data flow compensating709/236, Computer-to-computer data framing709/235, Congestion avoiding709/230, COMPUTER-TO-COMPUTER PROTOCOL IMPLEMENTING709/231, Computer-to-computer data streaming709/232Computer-to-computer data transfer regulatingExaminersPrimary: Lefkowitz, SumatiAttorney, Agent or FirmUS Patent References4144522, Electro-control system for data transmissionIssued on: 03/13/1979 Inventor: Kageyama , et al.4344171, Effective error control scheme for satellite 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method and apparatus and medium storing an error compensating program Issued on: 12/11/2001 Inventor: Yoshioka, et al.6335933, Limited automatic repeat request protocol for frame-based communication channels Issued on: 01/01/2002 Inventor: Mallory6389016, Data communication system and method for transporting data Issued on: 05/14/2002 Inventor: Sabaa, et al.6411621, Apparatus, method and system for an intermediate reliability protocol for network message transmission and reception Issued on: 06/25/2002 Inventor: Norton, et al.6425105, Bidirectional ARQ apparatus and method Issued on: 07/23/2002 Inventor: Piirainen, et al.6438105, Reliable internet facsimile protocol Issued on: 08/20/2002 Inventor: Qarni, et al.6473425, Mechanism for dispatching packets via a telecommunications network Issued on: 10/29/2002 Inventor: Bellaton, et al.6487689, Receiver initiated recovery algorithm (RIRA) for the layer 2 tunneling protocol (L2TP) Issued on: 11/26/2002 Inventor: Chuah6496481, Data transfer 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