Patent ReferencesStress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structure Plating of noble metal electrodes for DRAM and FRAM Method of fabricating shallow trench isolation structures using a oxidized polysilicon trench mask Method for removing silicon nitride in the fabrication of semiconductor devices Method of oxide etching with high selectivity to silicon nitride by using polysilicon layer Methods for making semiconductor devices having air dielectric interconnect structures Method to form a recess free deep contact Methods for shallow trench isolation Fabrication of gate and diffusion contacts in self-aligned contact process Easy to remove hard mask layer for semiconductor device fabrication InventorsAssigneeApplicationNo. 10045354 filed on 11/07/2001US Classes:438/694, Combined with coating step438/695, Simultaneous etching and coating438/697, Planarization by etching and coating438/709, Photo-induced plasma etching438/717, Utilizing multilayered mask438/738, Selectively etching substrate possessing multiple layers of differing etch characteristics438/404, Total dielectric isolation438/424, Grooved and refilled with deposited dielectric material438/619, Air bridge structure430/313, With formation of resist image, and etching of substrate or material deposition438/637, With formation of opening (i.e., viahole) in insulative layer438/745, Liquid phase etching438/253, Stacked capacitor430/314, Etching of substrate and material deposition438/692, Simultaneous (e.g., chemical-mechanical polishing, etc.)257/415, Physical deformation438/700, Formation of groove or trench438/305, Plural doping steps257/301, Capacitor in trench438/427Refilling multiple grooves of different widths or depthsExaminersPrimary: Coleman, W. DavidAssistant: Nguyen, Khiem Attorney, Agent or FirmInternational ClassH01L 21311AbstractOne aspect of the invention relates to a method of removing a hard mask from a surface, especially a silicon surface. The hard mask is removed by first applying a sacrificial coating and then plasma etching. The sacrificial material fills pattern gaps formed using the hard mask and protects insulators, such as oxides, within those pattern gaps. The sacrificial material is removed together with the hard mask by the plasma etching. The invention provides a process for removing hard masks from silicon layers without significantly damaging either the silicon layer or any exposed oxides and can be applied in a variety of integrated circuit device manufacturing processes, such as patterning the floating gate layer of a flash memory device. |
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