U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Innovative method of hard mask removal

Patent 6809033 Issued on October 26, 2004. Estimated Expiration Date: Icon_subject November 7, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Stress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structure
Patent #: 5270265
Issued on: 12/14/1993
Inventor: Hemmenway, et al.

Plating of noble metal electrodes for DRAM and FRAM
Patent #: 5789320
Issued on: 08/04/1998
Inventor: Andricacos, et al.

Method of fabricating shallow trench isolation structures using a oxidized polysilicon trench mask
Patent #: 5998278
Issued on: 12/07/1999
Inventor: Yu

Method for removing silicon nitride in the fabrication of semiconductor devices
Patent #: 6010949
Issued on: 01/04/2000
Inventor: Li, et al.

Method of oxide etching with high selectivity to silicon nitride by using polysilicon layer
Patent #: 6015757
Issued on: 01/18/2000
Inventor: Tsai, et al.

Methods for making semiconductor devices having air dielectric interconnect structures
Patent #: 6057224
Issued on: 05/02/2000
Inventor: Bothra, et al.

Method to form a recess free deep contact
Patent #: 6103455
Issued on: 08/15/2000
Inventor: Huang, et al.

Methods for shallow trench isolation
Patent #: 6159821
Issued on: 12/12/2000
Inventor: Cheng, et al.

Fabrication of gate and diffusion contacts in self-aligned contact process
Patent #: 6159844
Issued on: 12/12/2000
Inventor: Bothra

Easy to remove hard mask layer for semiconductor device fabrication
Patent #: 6261967
Issued on: 07/17/2001
Inventor: Athavale, et al.

More ...

Inventors

Assignee

Application

No. 10045354 filed on 11/07/2001

US Classes:

438/694, Combined with coating step438/695, Simultaneous etching and coating438/697, Planarization by etching and coating438/709, Photo-induced plasma etching438/717, Utilizing multilayered mask438/738, Selectively etching substrate possessing multiple layers of differing etch characteristics438/404, Total dielectric isolation438/424, Grooved and refilled with deposited dielectric material438/619, Air bridge structure430/313, With formation of resist image, and etching of substrate or material deposition438/637, With formation of opening (i.e., viahole) in insulative layer438/745, Liquid phase etching438/253, Stacked capacitor430/314, Etching of substrate and material deposition438/692, Simultaneous (e.g., chemical-mechanical polishing, etc.)257/415, Physical deformation438/700, Formation of groove or trench438/305, Plural doping steps257/301, Capacitor in trench438/427Refilling multiple grooves of different widths or depths

Examiners

Primary: Coleman, W. David
Assistant: Nguyen, Khiem

Attorney, Agent or Firm

International Class

H01L 21311

Abstract

One aspect of the invention relates to a method of removing a hard mask from a surface, especially a silicon surface. The hard mask is removed by first applying a sacrificial coating and then plasma etching. The sacrificial material fills pattern gaps formed using the hard mask and protects insulators, such as oxides, within those pattern gaps. The sacrificial material is removed together with the hard mask by the plasma etching. The invention provides a process for removing hard masks from silicon layers without significantly damaging either the silicon layer or any exposed oxides and can be applied in a variety of integrated circuit device manufacturing processes, such as patterning the floating gate layer of a flash memory device.

PatentsPlus Images
Enhanced PDF formats
loading...
PatentsPlus: add to cart
PatentsPlus: add to cartSearch-enhanced full patent PDF image
$9.95more info
 
Sign InRegister
Username  
Password   
forgot password?