U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Circuit arrangement and method for generating a time-limited signal

Patent 6806749 Issued on October 19, 2004. Estimated Expiration Date: Icon_subject September 12, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

CMOS Reset circuit
Patent #: 4405871
Issued on: 09/20/1983
Inventor: Buurma ,   et al.

Power-on reset circuit
Patent #: 4409501
Issued on: 10/11/1983
Inventor: Eickerman ,   et al.

Power supply potential rising detection circuit
Patent #: 5017803
Issued on: 05/21/1991
Inventor: Yoshida

Zero-consumption power-on reset circuit
Patent #: 5321317
Issued on: 06/14/1994
Inventor: Pascucci, et al.

Circuit for covering initial conditions when starting-up an integrated circuit device
Patent #: 5612641
Issued on: 03/18/1997
Inventor: Sali

Power-on reset circuit for resetting semiconductor integrated circuit Patent #: 5812001
Issued on: 09/22/1998
Inventor: Imamiya

Inventor

Assignee

Application

No. 10242880 filed on 09/12/2002

US Classes:

327/143, Responsive to power supply327/198, Initializing, resetting, or protecting a steady state condition327/227, Monostable327/546With field-effect transistor

Examiners

Primary: Callahan, Timothy P.
Assistant: Englund, Terry L.

Attorney, Agent or Firm

Foreign Patent References

  • 10024980 DE 11/01/2001
  • WO 9927652 WO 06/01/1999

International Classes

H03K 1722
H03K 3355
H03K 1722
H03L 700

Abstract

A circuit includes a second switching unit, a first switching unit that is connected to and selectively actuates the second switching unit, and a capacitive voltage divider including first, second and third capacitances connected in series. The first and second switching units are connected respectively to first and second junctions between the first and second and the second and third capacitances respectively. An associated method involves applying a supply voltage to the voltage divider so as to charge the first and second junctions, discharging the first junction through the first switching unit, which, dependent on the voltage of the first junction, selectively actuates the second switching unit to supply an additional charging current to the second junction. A time-limited signal such as a power-on reset signal is tapped from the first or second switching unit or from the second junction. Thereafter, the circuit draws no further current.

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