Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
Double gate semiconductor device having separate gates
Strained fin FETs structure and method Patent #: 6635909
ApplicationNo. 10349042 filed on 01/23/2003
US Classes:257/349, With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate257/192, Field effect transistor438/303, Utilizing gate sidewall structure257/365With plural, separately connected, gate electrodes in same device
ExaminersPrimary: Wilson, Neill R.
Attorney, Agent or Firm
International ClassH01L 2701
AbstractA semiconductor structure includes a fin and a layer formed on the fin. The fin includes a first crystalline material having a rectangular cross section and a number of surfaces. The layer is formed on the surfaces and includes a second crystalline material. The first crystalline material has a different lattice constant than the second crystalline material to induce tensile strain within the first layer.