Strained channel finfet

Patent 6803631 Issued on October 12, 2004. Estimated Expiration Date:

January 23, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
Patent #: 6475869
Issued on: 11/05/2002
Inventor: Yu

Double gate semiconductor device having separate gates
Patent #: 6611029
Issued on: 08/26/2003
Inventor: Ahmed , et al.

Strained fin FETs structure and method Patent #: 6635909
Issued on: 10/21/2003
Inventor: Clark , et al.

Inventors

Assignee

Advanced Micro Devices, Inc.

Application

No. 10349042 filed on 01/23/2003

US Classes:

257/349, With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate257/192, Field effect transistor438/303, Utilizing gate sidewall structure257/365With plural, separately connected, gate electrodes in same device

Examiners

Primary: Wilson, Neill R.

Attorney, Agent or Firm

Harrity & Snyder, LLP

International Class

H01L 2701

Abstract

A semiconductor structure includes a fin and a layer formed on the fin. The fin includes a first crystalline material having a rectangular cross section and a number of surfaces. The layer is formed on the surfaces and includes a second crystalline material. The first crystalline material has a different lattice constant than the second crystalline material to induce tensile strain within the first layer.

Other References

Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub 50-nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.