Patent ReferencesMethod for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation Data processor for reloading deferred pushes in a copy-back data cache Memory address translation system having modifiable and non-modifiable translation mechanisms Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system Method of measuring strain High speed video frame buffer Software controlled cache configuration based on average miss rate Patent #: 6681297 InventorsAssigneeApplicationNo. 10072925 filed on 02/12/2002US Classes:711/133, Entry replacement strategy711/144, Cache status data bit711/145Access control bitExaminersPrimary: Sparks, DonaldAssistant: Peugh, Brian R. International ClassG06F 1200AbstractIn response to determining a requested line of data is not stored within a local memory, the requested line of data is written to the local memory from a remote memory. Additionally, a victim page is selected in the local memory in response to the requested line of data not being in the local memory and it is determined whether one or more lines of the victim page are dirty. Furthermore, the one or more dirty lines are written to the remote memory in response to determining that the one or more lines are dirty and the requested line of data is fetched from the remote memory. Moreover, the requested line of data is stored within the page of data at a location previously occupied by the victim page.Other References
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