Method and device for address translation for compressed instructions
Patent 6779100 Issued on August 17, 2004. Estimated Expiration Date: December 17, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
711/202, Address mapping (e.g., conversion, translation)711/125, Instruction data cache711/217, Generating a particular pattern/sequence of addresses711/220, Combining two or more values to create address711/214, Operand address generation712/230Generating next microinstruction address
A computer system for storing corresponding instruction blocks in a compressed form in a main memory and in an uncompressed form in an instruction cache. The instruction cache line addresses for the uncompressed instruction blocks in the instruction cache have an algebraic correlation to the main memory line addresses for the compressed instruction blocks in the main memory. Preferably, the instruction cache line addresses are proportional to the corresponding main memory line addresses.
December 17, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
