U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Methods and apparatus for burst tolerant excessive bit error rate alarm detection and clearing

Patent 6775237 Issued on August 10, 2004. Estimated Expiration Date: Icon_subject March 29, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

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Apparatus and method employing a window reset for excessive bit error rate alarm detection and clearing
Patent #: 5724362
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Inventor: Lau

Bit error rate detection system
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Method for signal degradation alarm detection and cancellation in synchronous digital microwave system
Patent #: 5867096
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Inventors

Assignee

Application

No. 09912086 filed on 03/29/2001

US Classes:

370/241, DIAGNOSTIC TESTING (OTHER THAN SYNCHRONIZATION)370/244, Of a switching system370/907, Synchronous Optical network (SONET)375/224, TESTING714/48, Error detection or notification714/704Error count or rate

Examiners

Primary: Duong, Frank

Attorney, Agent or Firm

International Class

H04B 7208

Abstract

The excessive bit error rate detection algorithm operates in two modes: BURST mode and non-BURST mode. In non-BURST mode, an alarm state is entered if an error count exceeds a threshold within a set number of frames and exits the alarm state when the error count stays below a threshold for a set number of frames. In the BURST mode, the alarm state is not entered unless the error count exceeds the threshold two consecutive times and does not exit the alarm state unless the error rate remains below a threshold for two consecutive frame counts.

Other References

  • Bellcore document TR-NWT-000253 entitled “Synchronous optical network (SONET) Transport Systems: Common Generic Criteria”, Telecordia Technologies, GR-253-CORE, Issue 3, Sep. 2000.
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