Method for interconnection between transfer devices and storage capacitors in memory cells and device formed thereby
June 26, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesOne-device monolithic random access memory and method of fabricating same Method of fabricating random access memory device Method of making stacked E-cell capacitor DRAM cell MIS device having lightly doped drain structure Semiconductor device having an overlapping memory cell Isolated sidewall capacitor having a compound plate electrode Semiconductor memory device Patent #: 5670806 InventorsApplicationNo. 09105739 filed on 06/26/1998US Classes:438/254, Including selectively removing material to undercut and expose storage node layer438/256, Contacts formed by selective growth or deposition257/306, Stacked capacitor257/307, Parallel interleaved capacitor electrode pairs (e.g., interdigitized)257/308, With capacitor electrodes connection portion located centrally thereof (e.g., fin electrodes with central post)29/25, UMBRELLA-FRAME MAKING29/30, Planer29/42Fluid operatedExaminersPrimary: Pham, LongAssistant: Rao, Shrinivas H. Attorney, Agent or FirmInternational ClassesH01L 31119H01L 2100 H01L 218242 H01L 218236 AbstractThe preferred embodiment of the present invention provides unique structure for connecting between a storage capacitor and a transfer device in a memory cell and a method for fabricating the same. The preferred embodiment of the present invention forms a capacitor structure having a “lip” at its top on the side the connection is to be made. To form the connection, dopant is diffused from the lower surface of the capacitor step and into the substrate, forming a surface strap to connect between the storage capacitor and the transfer device. This surface strap has the advantage of being self aligned with the storage capacitor and the transfer device, facilitating higher memory cell densities. The present invention can be used to form connections between storage capacitors and memory cells in a wide variety of devices.Other References
Field of SearchStacked capacitorParallel interleaved capacitor electrode pairs (e.g., interdigitized) With capacitor electrodes connection portion located centrally thereof (e.g., fin electrodes with central post) HAVING MAGNETIC OR FERROELECTRIC COMPONENT Including selectively removing material to undercut and expose storage node layer Contacts formed by selective growth or deposition | |
