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US Patent 6760879 - System and method of turbo decoding

US Patent Issued on July 6, 2004
Estimated Patent Expiration Date: Icon_subject January 28, 2023Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
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Abstract

Methods and architectures for turbo decoding are presented. The methods are such that low energy consumption is obtained with reduced memory requirements. Moreover the methods show improved performance with respect to latency.

Other References

  • Halter S, et al. “Reconfigurable Signal Processor for Channel Cording & Decoding in Low SNR Wireless Communications.” IEEE Workshop in signal Processing Systems, SIPS, Design and Implementation, Oct. 8, 1998, pp. 260-264.
  • Hsu J-M, et al. “A Parallel Decoding Scheme for Turbo Codes.” ISCAS 1998. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, Monterey, CA, May 31-Jun. 3, 1998, New York, NY: IEEE, US, vol. 1, May 31, 1998, pp. 445-448.
  • Schurgers, et al. “Energy Efficient Data Transfer and Storage Organization for a MAP Turbo Decoder Module.” Proceedings 1999 International Symposium on Low Power Electronics and Design. San Diego, CA, Aug. 16-17, 1999, International Symposium on Low Power Electronics and Design, New York, NY: ACM, US, Aug. 16, 1999, pp. 76-81.
  • Viterbi A. J., “An Intuitive Justification and a Simplified Implementation of the Map Decoder for Convolutional Codes,” IEEE Journal on Selected Areas in Communications, IEEE Inc., New York, US vol. 16, No. 2, Feb. 1, 1998, pp. 260-264.
  • European Search Report. Application No. EP 00 20 0557. Date of Completion, May 28, 2002.
  • Joeressen, et al., “High-Speed VLSI Architectures for Soft-Output Viterbi Decoding”, vol. 8, No. 2, 1994 pps. 169-181.
  • Garrett, et al., “Low Power Architecture of the Soft-Output Viterbi Algorithm”, ISLPED 1998, pps. 262-267.
  • Berrou, et al., Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes (1), IEEE, 1993, pps. 1064-1070.
  • S. Pietrobon, “Efficient Implementation of Continuous MAP Decoders and a Synchronisation Technique for Turbo Decoders”, Int. Symp. on Inform Theory and its Applications, Sep. 1996, pps. 586-589.
  • Raouafi, et al. “Saving Memory in Turbo-Decoders Using the Max-Log-MAP Algorithm”, IEE Colloquium. Turbo Codes in Digital Broadcasting—Could it Double Capacity?, London, UK Nov. 22, 1999, pp. 14/1-4.
  • Giuletti, et al., “A Study on Fast, Low-Power VLSI Architectures for Turbo Codes”, IMEC, Belgium, 2000.
  • Shannon, C.E., “A Mathematical Theory of Communication”, Reprinted with corrections from The Bell System Technical Journal, vol. 27, pp. 379-423, 623-656, Jul., Oct., 1948.
  • Masera, et al., “VLSI Architecture for Turbo Codes”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, No. 3, Sep. 1999.
  • Bekooij, et al., “Power-Efficient Application-Specific VLIW Processor for Turbo Decoding”, ISSCC 2001, Session 12, Signal Processing for Storage and Coding, 12.1.
  • Hong, et al., Design and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications, Journal of VLSI Signal Processing Systems 24, 43-57 (2000).
  • 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Multiplexing and channel coding (FDD) (Release 1999).

Inventors

Assignee

Application

No. 10354262 filed on 01/28/2003

US Classes:

714/755, Double encoding codes (e.g., product, concatenated)714/786Forward error correction by tree code (e.g., convolutional)

Field of Search

714/755, Double encoding codes (e.g., product, concatenated)714/786, Forward error correction by tree code (e.g., convolutional)714/791, Sequential decoder (e.g., Fano or stack algorithm)714/793, Syndrome decodable (e.g., self orthogonal)714/794, Maximum likelihood714/795, Viterbi decoding375/340, Particular pulse demodulator or detector375/262, Maximum likelihood decoder or viterbi decoder375/265, Trellis encoder or Trellis decoder375/341Maximum likelihood decoder or viterbi decoder

Examiners

Primary: Decady, Albert
Assistant: Chase, Shelly A

Attorney, Agent or Firm

US Patent References

5721745, Parallel concatenated tail-biting convolutional code and decoder therefor
Issued on: 02/24/1998
Inventor: Hladik, et al.5933462, Soft decision output decoder for decoding convolutionally encoded codewords
Issued on: 08/03/1999
Inventor: Viterbi, et al.6023783, Hybrid concatenated codes and iterative decoding
Issued on: 02/08/2000
Inventor: Divsalar, et al.6252917, Statistically multiplexed turbo code decoder
Issued on: 06/26/2001
Inventor: Freeman6304995, Pipelined architecture to decode parallel and serial concatenated codes
Issued on: 10/16/2001
Inventor: Smith, et al.6484283Method and apparatus for encoding and decoding a turbo code in an integrated modem system
Issued on: 11/19/2002
Inventor: Stephen, et al.

Foreign Patent References

  • 0 827 284 EP 03/01/1998
  • WO 9613105 WO 05/01/1996

International Classes

H03M 1300
H03M 1303

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