Phase re-alignment of SONET/SDH network switch without pointer manipulation
April 20, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and means for transferring a data payload from a first SONET signal to a SONET signal of different frequency Pointer processing circuit in sonet system SONET DS-N desynchronizer Synchronous payload pointer processing system in digital data transmission network Telecommunication network node Sonet payload pointer processing and architecture Time division multiplexed synchronous state machine having state memory Optical switching unit and control method for same Telecommunications transmission Patent #: 5883900 InventorsAssigneeApplicationNo. 09553501 filed on 04/20/2000US Classes:370/541, Multiple levels of multiplexing to form a multiplex hierarchy370/394, Sequencing or resequencing of packets to insure proper output sequence order370/516Adjusting for phase or jitterExaminersPrimary: Vu, Huy D.Assistant: Philpott, Justin M. Attorney, Agent or FirmInternational ClassH04J 1408AbstractA large network switch has switch elements distributed across several chassis separated by perhaps several hundred meters. A generated sync pulse arrives at different switch elements at different times, creating skew. The latency of data through the network switch is set to match the frame period of SONET frames. SONET frames are adjusted at the ingress ports to align the data pointer to the beginning of the frame. The frame is divided along row boundaries into separate cell-packets that are routed across the switch fabric to the egress port. The packets are held in a buffer at the egress port until the next frame begins with the next sync pulse. Upon receiving the next sync pulse, the frame is transmitted. No pointer adjustment is needed by the egress port. A row number is used as a sequence number for the cell-packet to allow the egress port to re-order the cell-packets when transmitting the frame. Since no pointer manipulation is needed at the egress port, pointer management is simplified.Field of SearchRouting packets through a circuit switching networkHaving details of control storage arrangement Sequencing or resequencing of packets to insure proper output sequence order Utilizing a plurality of ATM networks (e.g., MPOA, SONET, or SDH) Detail of clock recovery or synchronization Having input or output storage or both Transmission time into time slots adjusted based upon propagation delay time Synchronization information is distributed over multiple frames Synchronization information is distributed within a frame Adjusting for phase or jitter Provide plural phases of a clocking signal Delay based upon propagation delay time Multiplexing plural input channels to a common output channel Plural input channels of same rate to a single common rate output channel Multiple levels of multiplexing to form a multiplex hierarchy | |
