Static pass transistor logic with transistors with multiple vertical gates
Patent 6744082 Issued on June 1, 2004. Estimated Expiration Date: May 30, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
257/213, FIELD EFFECT DEVICE257/348, Depletion mode field effect transistor257/392, Insulated gate field effect transistors of different threshold voltages in same integrated circuit (e.g., enhancement and depletion mode)257/393, Insulated gate field effect transistor adapted to function as load element for switching insulated gate field effect transistor257/402With permanent threshold adjustment (e.g., depletion mode)
Systems and methods are provided for static pass transistor logic having transistors with multiple vertical gates. The multiple vertical gates are edge defined such that only a single transistor is required for multiple logic inputs. Thus a minimal surface area is required for each logic input. The novel static pass transistor of the present invention includes a transistor which has a horizontal depletion mode channel region between a single source and drain region. A number of vertical gates are located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. At least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material. According to the present invention, there is no source nor drain region associated with each input and the gates have sub-lithographic horizontal dimensions by virtue of being edge defined vertical gates.
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May 30, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
