Digital cancellation of D/A converter noise in pipelined A/D converters
February 22, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesHigh-speed, high-resolution analog to digital converter subranging architecture Multi-bit oversampled DAC with dynamic element matching Multi-stage A/D converter Processor controlled analog-to-digital converter circuit Multi-stage delta sigma modulator with one or more high order sections Oversampled pipeline A/D converter with mismatch shaping Noise shaping dynamic element mismatch in analog to digital converters 2nd order noise shaping dynamic element matching for multibit data converters Pipelined analog to digital converter using digital mismatch noise cancellation Multistage analog-to-digital converter with amplifier component swapping for improved linearity Patent #: 6515611 InventorApplicationNo. 09792751 filed on 02/22/2001US Classes:341/161, Acting sequentially341/118CONVERTER COMPENSATIONExaminersPrimary: Wamsley, PatrickAttorney, Agent or FirmInternational ClassesH03M 106H03M 138 AbstractAn improvement to a conventional multistage pipelined Analog-to-Digital Converter (ADC) 1, the improvement directed to canceling noise resultant from component mismatch. The improved ADC 2 uses in at least a first, and preferably two, stages 21, 22: (i) a flash DAC 212, 222 of a dynamic element matching (DEM) type producing, as well as an associated intermediate analog signal, random bits and parity bits; (ii) a Digital Noise Cancellation (DNC) logic circuit 217, 227, receiving the random bits and the parity bits and a digitized residue sum of the digital output signals arising from all stages beyond a stage of which the DNC logic circuit 217, 227 is a part, so as to produce an error estimate for the stage; and (iii) a subtractor 218, 228 subtracting the error estimates of the DNC logic circuits 217, 227 from the combined digital output signal of all higher stages 22-24 in order to produce a corrected ADC digital output signal.Field of SearchCONVERTER COMPENSATIONCONVERTER CALIBRATION OR TESTING Acting sequentially Serial conversions with change in signal Differential encoder and/or decoder (e.g., delta modulation, differential pulse code modulation) Using charge coupled devices or switched capacitances Analog to digital conversion Including parallel paths (e.g., current mirror) With amplifier connected to or between current paths | |
