Reduction of storage elements in synthesized synchronous circuits
Patent 6704909 Issued on March 9, 2004. Estimated Expiration Date: 
June 19, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 19, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesEmulation system with time-multiplexed interconnect Efficient top-down characterization method Function unit allocation in processor design Programmatic synthesis of processor element arrays Method and apparatus for jump control in a pipelined processor Patent #: 6560754 InventorAssigneeApplicationNo. 10/176424 filed on 06/19/2002US Classes:716/1, CIRCUIT DESIGN716/18, Logical circuit synthesizer716/2Optimization (e.g., redundancy, compaction)ExaminersPrimary: Siek, VutheAssistant: Levin, Naum International ClassG06F 17/50 (20060101)AbstractMethod and apparatus for reducing a number of storage elements in a synthesized synchronous circuit. In one embodiment, the circuit is represented as a directed, partitioned graph. The graph is divided into a plurality of time-ordered time slots that are bounded by storage elements. The strongly-connected components (SCCs) in the graph are first identified. For each middle SCC where there is slack between the middle SCC and a first SCC and slack between the middle SCC and a second SCC, a time-slot-relative direction is selected for moving the middle SCC. The direction is selected as a function of a number of storage elements required for moving the middle SCC toward the first SCC versus moving the middle SCC toward the second SCC. The middle SCC is then moved in the selected time-slot-relative direction.Other References
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