Charge pump with improved reliability
June 26, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSubstrate bias generator with power supply control means to sequence application of bias and power to prevent CMOS SCR latch-up Pulse drive circuit Internal voltage converter in semiconductor integrated circuit Charge pump circuit for a substrate voltage generator of a semiconductor memory device Voltage generating circuit causing no threshold voltage loss by FET in output voltage Voltage multiplier Dual back-bias voltage generating circuit with switched outputs Voltage generating circuit in semiconductor integrated circuit Voltage transfer circuit and a booster circuit, and an IC card comprising the same Voltage boosting circuit having cross-coupled precharge circuits InventorAssigneeApplicationNo. 10/179222 filed on 06/26/2002US Classes:327/536, Charge pump details327/537With field-effect transistorExaminersPrimary: Cunningham, Terry D.Attorney, Agent or FirmInternational ClassesG11C 5/14 (20060101)H02M 3/07 (20060101) H02M 3/04 (20060101) Foreign Application Priority Data1999-05-17 JPAbstractA semiconductor integrated circuit device having an internal voltage generating circuit which generates a voltage two or more times higher than an operating voltage while at the same time reducing the voltage applied to a device, thereby ensuring the device reliability. In a charge pump circuit driven by supply voltage VDD, a maximum of 2VDD or a similar level voltage is applied between the drain and source of a MOSFET, the MOSFET being connected in series with a conduction MOSFET of the same type, the gate of which is supplied with VD-VDD, or a potential which is VDD lower than VD, the drain potential before its connection. The gate potential is obtained directly from a node in said charge pump which generates a voltage pulse synchronized with the voltage between the drain and source of that MOSFET, or through another rectifier device branched via a capacitor from the node. | |
