Method for the linear configuration of metallic fuse sections on wafers

Patent 6698086 Issued on March 2, 2004. Estimated Expiration Date:

September 30, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Inventor

Klette, Rudiger

Assignee

Infineon Technologies AG

Application

No. 09/163874 filed on 09/30/1998

US Classes:

29/623, Fuse making257/E21.526, Connection or disconnection of subentities or redundant parts of device in response to measurement, e.g., wafer scale, memory devices (EPO)257/E23.146, With adaptable interconnections (EPO)257/E23.179, Marks applied to semiconductor devices or parts, e.g., registration marks, test patterns, alignment structures, wafer maps (EPO)29/825, Conductor or circuit manufacturing337/160, With fusible metal overlay (e.g., alloy-forming)337/198, Prong or blade (e.g., plug-type housing)337/297With nonconductive core (e.g., printed circuit)

Examiners

Primary: Vo, Peter
Assistant: Trinh, Michael

Attorney, Agent or Firm

International Classes

H01L 23/544 (20060101)
H01L 23/52 (20060101)
H01L 21/66 (20060101)
H01L 23/525 (20060101)

Foreign Application Priority Data

1997-09-30 DE

Abstract

Linear configurations of metallic fuse sections have a bit combination which represents a characteristic of a circuit on a wafer. The metallic fuse sections need to be rid of a polyimide layer covering them in order to make it possible to burn the fuse sections. In the event of unsatisfactory adherence to process parameters and insufficient removal of polyimide on the metallic fuse sections, a resulting relative error in a characteristic of the circuit is minimized according to the method since the fuse section corresponding to the most significant bit is neighbored on both sides by other fuse sections.