U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Low-voltage differential I/O device

Patent 6696852 Issued on February 24, 2004. Estimated Expiration Date: Icon_subject July 25, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Low voltage swing output MOS circuit for driving an ECL circuit
Patent #: 5216297
Issued on: 06/01/1993
Inventor: Proebsting

Self biased low-voltage differential signal detector
Patent #: 5726592
Issued on: 03/10/1998
Inventor: Schulte, et al.

Differential high speed driver for low voltage operation
Patent #: 5898297
Issued on: 04/27/1999
Inventor: Bosnyak, et al.

High speed digital bus termination
Patent #: 5926031
Issued on: 07/20/1999
Inventor: Wallace, et al.

Method and apparatus for controlling the common-mode output voltage of a differential buffer
Patent #: 5939904
Issued on: 08/17/1999
Inventor: Fetterman, et al.

Low voltage differential driver with multiple drive strengths
Patent #: 5949253
Issued on: 09/07/1999
Inventor: Bridgewater, Jr.

Low voltage differential swing driver circuit
Patent #: 6025742
Issued on: 02/15/2000
Inventor: Chan

Differential output circuit
Patent #: 6028467
Issued on: 02/22/2000
Inventor: Burrows, et al.

Line receiver circuit having termination impedances with transmission gates connected in parallel
Patent #: 6037798
Issued on: 03/14/2000
Inventor: Hedberg

Driver circuit for high speed data
Patent #: 6194949
Issued on: 02/27/2001
Inventor: Hogeboom

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Inventor

Assignee

Application

No. 09/626264 filed on 07/25/2000

US Classes:

326/30, Bus or line termination (e.g., clamping, impedance matching, etc.)326/86Bus driving

Examiners

Primary: Lam, Tuan T.

Attorney, Agent or Firm

International Class

H04L 25/02 (20060101)

Abstract

A low voltage differential I/O device and method is modeled using voltage sources and voltage dividers, rather than the current source and sink model of the prior art. In an exemplary implementation, a driver includes two pairs of transistors coupled between voltage sources, each pair associated with a respective logic state. Depending on the logic state to be signaled, one pair of transistors is driven strongly while the other pair is turned off. A differential voltage is established across the true and complement signal lines, the polarity of which is determined by which pair of transistors is driven, and the magnitude of which is readily determined by voltage division of the voltage sources across known resistances. The driver of the invention offers stable and low impedance across both logic states and common mode. Moreover, active devices and feedback are not required to establish a common mode voltage or impedance as in the prior art.

Other References

  • National Semiconductor "Product Folder, DS90LV048A", Jun. 1999
  • National Semiconductor "LVDS Products, LVDS Product Family Introductions", Jun. 1999
  • National Semiconductor "Product Folder, DS90LV031A", Jun. 1999
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