U.S. patents available from 1976 to present.
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Object code compression using different schemes for different instruction types

Patent 6691305 Issued on February 10, 2004. Estimated Expiration Date: Icon_subject April 21, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Method and apparatus for compression, decompression, and execution of program code
Patent #: 6216213
Issued on: 04/10/2001
Inventor: Breternitz, Jr., et al.

Method and system for scope-based compression of register and literal encoding in a reduced instruction set computer (RISC)
Patent #: 6233674
Issued on: 05/15/2001
Inventor: Elnozahy

Dynamic microcode for embedded processors Patent #: 6263429
Issued on: 07/17/2001
Inventor: Siska

Inventors

Assignee

Application

No. 09/556927 filed on 04/21/2000

US Classes:

717/136, Translation of code710/68, Data compression and expansion712/41RISC

Examiners

Primary: Kim, Kenneth S.

Attorney, Agent or Firm

International Classes

G06F 9/30 (20060101)
G06F 9/45 (20060101)

Abstract

A code compression method for system-level power optimization that lessens the requirements imposed on main memory size. The method reduces the power consumption of a complete system comprising a CPU, instruction cache, data cache, main memory, data buses and address bus. The method includes extracting compressible instruction and data portions from executable code, creating a mathematical model of the extracted code portions, class the individual instructions in the extracted portions based upon their operation codes and compressing the instructions. The compressed instructions are further compressed when extracted from memory by using bus compaction. The method is also embodied in a computer system with a processor and a memory adapted to perform the steps of the method to compress the extracted instruction portions. Additionally, the method is embodied on a computer program product bearing software instructions adapted to perform the steps of the method to compress the extracted instruction portions. The invention also has an apparatus utilizing a post-cache architecture that has a decompression engine that decompresses instructions that have been compressed using the method of the invention. The apparatus extracts the compressed instructions from memory or the instruction/data cache using a bus compression technique to save power as the compressed instructions/data traverses the bus.

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