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US Patent 6678843 - Method and apparatus for interleaving, deinterleaving and combined interleaving-deinterleaving

US Patent Issued on January 13, 2004
Estimated Patent Expiration Date: Icon_subject May 17, 2022Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
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Abstract

Methods and apparatus wherein subsequent permutation and inverse permutation operations provide inputs in correct order for first and second processes. Processes needing inputs in original order and processes needing inputs in permutated order can be distinguished, thereby using one of the processes as reference process. Permutation and inverse permutation operations which can fit into a turbo coding system and in systems applying the turbo coding principle. At least one permutation and one inverse permutation operation can be performed subsequently. Permutation and inverse permutation operations may be altered by scheduling linear writing and reading operation and permutated or inverse permutated writing and reading operations. These methods enable parallel execution of sub-processes, where the processes producing and consuming data can be performed in a parallel way, and the writing and reading operations to and from a memory can be performed in a parallel way.

Other References

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  • Schurgers, et al. "Energy Efficient Data Transfer and Storage Organization for a MAP Turbo Decoder Module." Proceedings 1999 International Symposium on Low Power Electronics and Design. San Diego, CA, Aug. 16-17, 1999, International Symposium on Low Power Electronics and Design, New York, NY: ACM, US, Aug. 16, 1999, pp. 76-81
  • Viterbi A. J., "An Intuitive Justification and a Simplified Implementation of the Map Decoder for Convolutional Codes," IEEE Journal on Selected Areas in Communications, IEEE Inc., New York, US vol. 16, No. 2, Feb. 1, 1998, pp. 260-264
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Inventors

Assignee

Application

No. 10/151700 filed on 05/17/2002

US Classes:

714/701, Data formatting to improve error detection correction capability714/786Forward error correction by tree code (e.g., convolutional)

Field of Search

714/786, Forward error correction by tree code (e.g., convolutional)714/755, Double encoding codes (e.g., product, concatenated)714/795Viterbi decoding

Examiners

Primary: Decady, Albert
Assistant: Chase, Shelly A

Attorney, Agent or Firm

US Patent References

5721745, Parallel concatenated tail-biting convolutional code and decoder therefor
Issued on: 02/24/1998
Inventor: Hladik, et al.
5933462, Soft decision output decoder for decoding convolutionally encoded codewords
Issued on: 08/03/1999
Inventor: Viterbi, et al.
6023783, Hybrid concatenated codes and iterative decoding
Issued on: 02/08/2000
Inventor: Divsalar, et al.
6304995Pipelined architecture to decode parallel and serial concatenated codes
Issued on: 10/16/2001
Inventor: Smith, et al.

International Classes

H03M 13/00 (20060101)
H03M 13/45 (20060101)
H03M 13/29 (20060101)
H04L 1/00 (20060101)

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