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Method and apparatus for interleaving, deinterleaving and combined interleaving-deinterleaving

Patent 6678843 Issued on January 13, 2004. Estimated Expiration Date: Icon_subject May 17, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Parallel concatenated tail-biting convolutional code and decoder therefor
Patent #: 5721745
Issued on: 02/24/1998
Inventor: Hladik, et al.

Soft decision output decoder for decoding convolutionally encoded codewords
Patent #: 5933462
Issued on: 08/03/1999
Inventor: Viterbi, et al.

Hybrid concatenated codes and iterative decoding
Patent #: 6023783
Issued on: 02/08/2000
Inventor: Divsalar, et al.

Pipelined architecture to decode parallel and serial concatenated codes Patent #: 6304995
Issued on: 10/16/2001
Inventor: Smith, et al.

Inventors

Assignee

Application

No. 10/151700 filed on 05/17/2002

US Classes:

714/701, Data formatting to improve error detection correction capability714/786Forward error correction by tree code (e.g., convolutional)

Examiners

Primary: Decady, Albert
Assistant: Chase, Shelly A

Attorney, Agent or Firm

International Classes

H03M 13/00 (20060101)
H03M 13/45 (20060101)
H03M 13/29 (20060101)
H04L 1/00 (20060101)

Abstract

Methods and apparatus wherein subsequent permutation and inverse permutation operations provide inputs in correct order for first and second processes. Processes needing inputs in original order and processes needing inputs in permutated order can be distinguished, thereby using one of the processes as reference process. Permutation and inverse permutation operations which can fit into a turbo coding system and in systems applying the turbo coding principle. At least one permutation and one inverse permutation operation can be performed subsequently. Permutation and inverse permutation operations may be altered by scheduling linear writing and reading operation and permutated or inverse permutated writing and reading operations. These methods enable parallel execution of sub-processes, where the processes producing and consuming data can be performed in a parallel way, and the writing and reading operations to and from a memory can be performed in a parallel way.

Other References

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