Abstract

Methods and apparatus wherein subsequent permutation and inverse permutation operations provide inputs in correct order for first and second processes. Processes needing inputs in original order and processes needing inputs in permutated order can be distinguished, thereby using one of the processes as reference process. Permutation and inverse permutation operations which can fit into a turbo coding system and in systems applying the turbo coding principle. At least one permutation and one inverse permutation operation can be performed subsequently. Permutation and inverse permutation operations may be altered by scheduling linear writing and reading operation and permutated or inverse permutated writing and reading operations. These methods enable parallel execution of sub-processes, where the processes producing and consuming data can be performed in a parallel way, and the writing and reading operations to and from a memory can be performed in a parallel way.

Other References

• Halter S, et al. "Reconfigurable signal Processor for Channel Cording & Decoding in Low SNR Wireless Communications." IEEE Workshop in Signal Processing Systems, SIPS, Design and Implementation, Oct. 8, 1998, pp. 260-274
• Hsu J-M, et al. "A Parallel Decoding Scheme for Turbo Codes." ISCAS 1998. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, Monterey, CA, May 31--Jun. 3, 1998, New York, NY: IEEE, US, vol. 1, May 31, 1998, pp. 445-448
• Schurgers, et al. "Energy Efficient Data Transfer and Storage Organization for a MAP Turbo Decoder Module." Proceedings 1999 International Symposium on Low Power Electronics and Design. San Diego, CA, Aug. 16-17, 1999, International Symposium on Low Power Electronics and Design, New York, NY: ACM, US, Aug. 16, 1999, pp. 76-81
• Viterbi A. J., "An Intuitive Justification and a Simplified Implementation of the Map Decoder for Convolutional Codes," IEEE Journal on Selected Areas in Communications, IEEE Inc., New York, US vol. 16, No. 2, Feb. 1, 1998, pp. 260-264
• European Search Report. Application No. EP 00 20 0557. Date of Completion, May 28, 2002
• Joeressen, et al., "High-Speed VLSI Architectures for Soft-Output Viterbi Decoding", Vol. 8, No. 2, 1994 pp. 169-181
• Garrett, et al., "Low Power Architecture of the Soft-Output Viterbi Algorithm", ISLPED 1998, pp. 262-267
• Berrou, et al., Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes (1), IEEE, 1993, pp. 1064-1070
• S. Pietrobon, "Efficient Implementation of Continuous MAP Decoders and a Synchronisation Technique for Turbo Decoders", Int. Symp. on Inform, Theory and its Applications, Sep., 1996, pp. 586-589
• Raouafi, et al. "Saving Memory in Turbo-Decoders Using the Max-Log-MAP Algorithm", IEE Colloquium. Turbo Codes in Digital Broadcasting--Could it Double Capacity?, London, UK 22 Nov. 1999, pp. 14/1-4
• Giulietti, et al., "A Study on Fast, Low-Power VLSI Architectures for Turbo Codes", IMEC, Belgium
• Shannon, C.E., "A Mathematical Theory of Communication", Reprinted with corrections from The Bell System Technical Journal, vol. 27, pp. 379-423, 623-656, Jul., Oct., 1948
• Berrou, et al., Near Shannon Limit Error--Correcting Coding and Decoding: Turbo-Codes, IEEE, 1993
• Masera, et al., "VLSI Architecture for Turbo Codes", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, No. 3, Sep. 1999
• Bekooij, et al., "Power-Efficient Application-Specific VLIW Processor for Turbo Decoding", ISSCC 2001, Session 12, Signal Processing for Storage and Coding, 12.1
• Hong, et al., Design and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications, Journal of VLSI Signal Processing Systems 24, 43-57 (2000)
• 3^rd Generation Partnership Project; Technical Specification Group Radio Access Network; Multiplexing and channel coding (FDD) (Release 1999)