Integrated circuit defect review and classification process
August 5, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesApparatus for detecting defects in patterns Surface inspection scanning system Defect detection method of semiconductor wafer patterns Method of and apparatus for checking geometry of multi-layer patterns for IC structures Semiconductor integrated circuit chip having an identification circuit therein Method and apparatus for low angle, high resolution surface inspection Method for characterizing failed circuits on semiconductor wafers Semiconductor device having identification region for carrying out failure analysis Method for identifying a semiconductor die using an IC with programmable links Method and system for automated analysis of semiconductor defect data InventorApplicationNo. 10/213129 filed on 08/05/2002US Classes:356/237.4, On patterned or topographical surface (e.g., wafer, mask, circuit board)250/310, Electron probe type356/237.5, On patterned or topographical surface (e.g., wafer, mask, circuit board)356/394With comparison to master, desired shape, or reference voltageExaminersPrimary: Pham, Hoa Q.Attorney, Agent or FirmInternational ClassesG01N 21/95 (20060101)G01N 21/88 (20060101) AbstractThe present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprises the steps of visually inspecting the dice on the wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of the dice on the wafer, and determining if the wafer is acceptable to proceed in the manufacturing process.Field of SearchINSPECTION OF FLAWS OR IMPURITIESSurface condition Detection of object or particle on surface On patterned or topographical surface (e.g., wafer, mask, circuit board) On patterned or topographical surface (e.g., wafer, mask, circuit board) Transparent or translucent material Patterned surface Surface condition Detection of an object or particle on surface With comparison to master, desired shape, or reference voltage | |
