Method and apparatus for automated generation of test semiconductor wafers
May 22, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod for setting and adjusting process parameters to maintain acceptable critical dimensions across each die of mass-produced semiconductor wafers Monitoring apparatus and method particularly useful in photolithographically processing substrates Low cost application of oxide test wafer for defect monitor in photolithography process Method and apparatus for adaptive process control of critical dimensions during spin coating process Method and apparatus for fault detection and control Method and apparatus for compensating for critical dimension variations in the production of a semiconductor wafer Semiconductor processing techniques Patent #: 6303395 InventorAssigneeApplicationNo. 09/577403 filed on 05/22/2000US Classes:700/121, Integrated circuit production or semiconductor fabrication700/110Defect analysis or recognitionExaminersPrimary: Picard, Leo P.Assistant: Rapp, Chad Attorney, Agent or FirmInternational ClassG01R 31/28 (20060101)AbstractThe present invention provides for a method and an apparatus for automated generation of test semiconductor wafers. At least one process run of semiconductor devices is performed. A determination is made whether an excursion of the process exists. An automated test wafer generation process is performed in response to the determination that an excursion of the process exists. A control parameter modification sequence is implemented in response to an examination of the test wafers. | |
