Clocked pass transistor and complementary pass transistor logic circuits

Patent 6646474 Issued on November 11, 2003. Estimated Expiration Date:

August 15, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Time multiplexed ratioed logic
Patent #: 5612638
Issued on: 03/18/1997
Inventor: Lev

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Inventor: Inui

Inventor

Forbes, Leonard

Application

No. 10/218511 filed on 08/15/2002

US Classes:

326/98, MOSFET326/113, Pass transistor logic or transmission gate logic326/17, ACCELERATING SWITCHING326/95, Field-effect transistor327/208, Including field-effect transistor327/214, Complementary transistors327/224With single semiconductor device

Examiners

Primary: Tokar, Michael
Assistant: Tan, Vibol

Attorney, Agent or Firm

Dickstein Shapiro Morin & Oshinsky LLP

International Classes

H03K 19/096 (20060101)
H04L 25/02 (20060101)

Abstract

A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. The logic circuit includes a pass transistor logic circuit, a CMOS transistor pair connected as an inverter and having an input coupled to the output of the pass transistor logic circuit, a clocking transistor coupled between the inverter and a potential terminal to selectively enable the inverter according to a first clocking signal, and a precharge transistor coupled between the inverter output and a potential terminal to precharge the inverter output low according to a second clocking signal.

Other References

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