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US Patent 6642543 - Thin and thick gate oxide transistors on a functional block of a CMOS circuit residing within the core of an IC chip

US Patent Issued on November 4, 2003
Estimated Patent Expiration Date: Icon_subject September 26, 2020Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
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Abstract

A functional block for a CMOS circuit within the core of an integrated circuit chip and a method of making the same is disclosed. The functional block uses both thick and thin gate oxide transistors which reduces the leakage current and increases the voltage swing while permitting the device scaling in circuits made in CMOS technology. Within the functional block, the distance between a thick oxide transistor and a thin oxide transistor is chosen based on a transistor stability criterion. The thick and thin oxide transistors can be connected to identical or different voltage sources. Further, a transistor within a functional block can be chosen to be thick or thin oxide transistor based on a leakage current threshold or a voltage swing threshold.

Other References

  • Hon-Sum Wong, "Technology and device scaling considerations for CMOS imagers," IEEE Transactions on Electron Device, vol. 43, No. 12, Dec. 1996
  • E. R. Fossum, "CMOS image sensors: electronic camera-on-chip," IEEE Transactions on Electron Device, vol. 44, No. 10, Oct. 1996
  • N. Stevanovic et al., "A CMOS image sensor for high speed imaging," ISSCC Dig. Tech. Papers, pp. 104-105, Feb. 2000
  • S. Kleinfelder et al., "A 10,000 frames/s 0.18μM CMOS digital pixel sensor with pixel-level memory," ISSCC Dig. Tech. Papers, Feb. 2001
  • A. El. Gamal et al., "Pixel level processing why?, what?, and how?" Proceedings of the SPIE, vol. 3650, pp. 2-13, Jan. 1999
  • "Physical Verification Manufacturability & Analysis," 2.2 The CMOS Process, pp 1-6, retrieved on May 15, 2002. Retrieved from the internet:
  • H.-S. Philip Wong, "Beyond the Conventional MOSFET," retrieved on May 15, 2002. Retrieved from the internet:
  • Prof. Bernd-Peter Paris, Dec. 14, 1998, "CMOS Logic Gates," retrieved on May 15, 2002. Retrieved for the internet:
  • Dennis Sylvester, "The Rise (and Fall?) of CMOS in VLSI Design," Univ. of Mitchigan, Feb. 20, 2002, retrieved from the internet:URL:http://www.wwcs.umich.edu/~dennis/talks/ieee 022002.pdg on May 15, 2002
  • A. Krymski et al., "A High Speed 500 Frames/s, 1024×1024 CMOS Active Pixel Sensor," 1999 Symposium on VLSI Circuits Digest of Technical Papers

Inventors

Assignee

Application

No. 09/670484 filed on 09/26/2000

US Classes:

257/72, In array having structure for use as imager or display, or with transparent electrode257/291, Imaging array257/296, Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)257/E27.064Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS (EPO)

Field of Search

257/351, Complementary field effect transistor structures only (i.e., not including bipolar transistors, resistors, or other components)257/357, In complementary field effect transistor integrated circuit257/369, Complementary insulated gate field effect transistors257/370, Combined with bipolar transistor257/371, Complementary transistors in wells of opposite conductivity types more heavily doped than the substrate region in which they are formed, e.g., twin wells257/390, Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM))257/274, Complementary junction field effect transistors257/72, In array having structure for use as imager or display, or with transparent electrode257/296, Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)257/291Imaging array

Examiners

Primary: Abraham, Fetsum

Attorney, Agent or Firm

US Patent References

5266507, Method of fabricating an offset dual gate thin film field effect transistor
Issued on: 11/30/1993
Inventor: Wu
5293052, SOT CMOS device having differentially doped body extension for providing improved backside leakage channel stop
Issued on: 03/08/1994
Inventor: Cherne, et al.
5604150, Channel-stop process for use with thick-field isolation regions in triple-well structures
Issued on: 02/18/1997
Inventor: Mehrad
5960319, Fabrication method for a semiconductor device
Issued on: 09/28/1999
Inventor: Iwata, et al.
6051509, Semiconductor integrated circuit manufacturing method and device
Issued on: 04/18/2000
Inventor: Tsuchiaki
6060510, Triglycerides and ethyl esters of phenylalkanoic acid and phenylalkenoic acid useful in the treatment of various disorders
Issued on: 05/09/2000
Inventor: Brusilow
6278131, Pixel TFT and driver TFT having different gate insulation width
Issued on: 08/21/2001
Inventor: Yamazaki, et al.
6307236Semiconductor integrated circuit device
Issued on: 10/23/2001
Inventor: Matsuzaki, et al.

International Classes

H01L 27/092 (20060101)
H01L 27/085 (20060101)

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