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AbstractA functional block for a CMOS circuit within the core of an integrated circuit chip and a method of making the same is disclosed. The functional block uses both thick and thin gate oxide transistors which reduces the leakage current and increases the voltage swing while permitting the device scaling in circuits made in CMOS technology. Within the functional block, the distance between a thick oxide transistor and a thin oxide transistor is chosen based on a transistor stability criterion. The thick and thin oxide transistors can be connected to identical or different voltage sources. Further, a transistor within a functional block can be chosen to be thick or thin oxide transistor based on a leakage current threshold or a voltage swing threshold.Other References
| InventorsAssigneeApplicationNo. 09/670484 filed on 09/26/2000US Classes:257/72, In array having structure for use as imager or display, or with transparent electrode257/291, Imaging array257/296, Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)257/E27.064Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS (EPO)Field of Search257/351, Complementary field effect transistor structures only (i.e., not including bipolar transistors, resistors, or other components)257/357, In complementary field effect transistor integrated circuit257/369, Complementary insulated gate field effect transistors257/370, Combined with bipolar transistor257/371, Complementary transistors in wells of opposite conductivity types more heavily doped than the substrate region in which they are formed, e.g., twin wells257/390, Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM))257/274, Complementary junction field effect transistors257/72, In array having structure for use as imager or display, or with transparent electrode257/296, Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)257/291Imaging arrayExaminersPrimary: Abraham, FetsumAttorney, Agent or FirmUS Patent References5266507, Method of fabricating an offset dual gate thin film field effect transistorIssued on: 11/30/1993 Inventor: Wu5293052, SOT CMOS device having differentially doped body extension for providing improved backside leakage channel stop Issued on: 03/08/1994 Inventor: Cherne, et al.5604150, Channel-stop process for use with thick-field isolation regions in triple-well structures Issued on: 02/18/1997 Inventor: Mehrad5960319, Fabrication method for a semiconductor device Issued on: 09/28/1999 Inventor: Iwata, et al.6051509, Semiconductor integrated circuit manufacturing method and device Issued on: 04/18/2000 Inventor: Tsuchiaki6060510, Triglycerides and ethyl esters of phenylalkanoic acid and phenylalkenoic acid useful in the treatment of various disorders Issued on: 05/09/2000 Inventor: Brusilow6278131, Pixel TFT and driver TFT having different gate insulation width Issued on: 08/21/2001 Inventor: Yamazaki, et al.6307236Semiconductor integrated circuit device Issued on: 10/23/2001 Inventor: Matsuzaki, et al. International ClassesH01L 27/092 (20060101)H01L 27/085 (20060101) |