Silicide MOSFET architecture and method of manufacture
August 8, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesField effect semiconductor device Method for forming a transistor having silicided regions Method for fabricating double silicide gate electrode structures on CMOS-field effect transistors Method for fabricating a semiconductor device Method of forming deep sub-micron CMOS transistors with self-aligned silicided contact and extended S/D junction Silicide formation using two metalizations Dual silicide process to reduce gate resistance Patent #: 6391767 InventorsAssigneeApplicationNo. 10/215171 filed on 08/08/2002US Classes:438/303, Utilizing gate sidewall structure257/E21.413, Lateral single gate single channel transistor with noninverted structure, i.e., channel layer is formed before gate (EPO)257/E21.439, Providing different silicide thicknesses on gate and on source or drain (EPO)257/E21.703, Substrate is semiconductor body (EPO)257/E27.112, Including insulator on semiconductor, e.g. SOI (silicon on insulator) (EPO)257/E29.147, For thin-film silicon (EPO)257/E29.278, With LDD structure or extension or offset region or characterized by doping profile (EPO)257/E29.281, For preventing kink or snapback effect (e.g., discharging minority carriers of channel region for preventing bipolar effect) (EPO)438/151, Having insulated gate438/197, Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.)438/231, Plural doping steps438/306, Plural doping steps438/311, On insulating substrate or layer (i.e., SOI type)438/366, Having sidewall438/514, Ion implantation of dopant into semiconductor region438/533, And contact formation (i.e., metallization)438/542, Diffusing a dopant438/559, Using capping layer over dopant source to prevent out-diffusion of dopant438/560, Plural diffusion stages438/595, Having sidewall structure438/630, Silicide formation438/652, Plural layered electrode or conductor438/656, Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)438/682, Silicide438/952Utilizing antireflective layerExaminersPrimary: Niebling, John F.Assistant: Isaac, Stanetta Attorney, Agent or FirmInternational ClassesH01L 29/786 (20060101)H01L 21/02 (20060101) H01L 29/45 (20060101) H01L 27/12 (20060101) H01L 21/336 (20060101) H01L 21/70 (20060101) H01L 21/84 (20060101) H01L 29/66 (20060101) H01L 29/40 (20060101) AbstractThe present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in conjunction with SOI type device architecture.Field of SearchHaving insulated gateHaving insulated gate (e.g., IGFET, MISFET, MOSFET, etc.) Plural doping steps Utilizing gate sidewall structure Plural doping steps On insulating substrate or layer (i.e., SOI type) Having sidewall And contact formation (i.e., metallization) Ion implantation of dopant into semiconductor region Diffusing a dopant Using capping layer over dopant source to prevent out-diffusion of dopant Plural diffusion stages Having sidewall structure Silicide formation Plural layered electrode or conductor Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof) Silicide Utilizing antireflective layer | |
