Patent ReferencesCaching FIFO and method therefor First-in-first-out buffer memory Branch instruction handling in a self-timed marking system Asynchronous, dual-port, RAM-based FIFO with bi-directional address synchronization Decomposition of instructions into branch and sequential code sections Programming paradigm and microprocessor architecture for exact branch targeting Method for reducing branch target storage by calculating direct branch targets on the fly Pipeline elements which verify predecode information Patent #: 6502185 InventorsApplicationNo. 09/596280 filed on 06/19/2000US Classes:712/238Branch target bufferExaminersPrimary: Treat, William M.Attorney, Agent or FirmInternational ClassG06F 9/38 (20060101)AbstractThe speed of processing of a sequence of indirect branch instructions in a pipelined processor is increased by overlapping the latencies in the sequence of indirect branch instructions. The architecture of a digital processor is modified to include a link pipe system that allows the sequence of branch addresses required by the indirect branches to be written to a single location within the processor, and to be read from a single location in the processor. The link pipe system contains a plurality of registers (3, 5 & 7) for storage of respective branch target addresses. Each WRITE of a branch address is automatically directed (9) to individual registers within the link pipe system for storing the respective branch addresses; and each READ of a branch address is automatically directed (11) to the register containing the earliest WRITE of an address that was not previously read by the processor, whereby branch target addresses are retrieved on a "first in, first out" basis. | |