Test array and method for testing memory arrays
Patent 6639859 Issued on October 28, 2003. Estimated Expiration Date: 
October 25, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 25, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesStacked bit-line architecture for high density cross-point memory cell array Low cost, highly parallel memory tester Short-tolerant resistive cross point array Techniques for addressing cross-point diode memory arrays Patent #: 6552409 InventorAssigneeApplicationNo. 09/983697 filed on 10/25/2001US Classes:365/201, Testing365/214, Particular wiring365/230.03Plural blocks or banksExaminersPrimary: Le, Vu A.International ClassesG11C 29/48 (20060101)G11C 29/04 (20060101) G11C 29/18 (20060101) AbstractA test array includes row conductors, column conductors, and memory cells located at crossing points of the row and column conductors. The test array can have groups of the row conductors or the column conductors electrically coupled, or ganged together, so that they share common terminals. Other selected row and column conductors can have individual terminals. In this configuration, memory cells located at the intersection of row and column conductors that have individual terminals can have their characteristics measured using a test apparatus. Ganging together groups of row or column conductors means that the test array has fewer terminals for connection to the test apparatus. Therefore, a test apparatus having a limited number of probes for connection to test array terminals can be used to test arrays of various sizes. | |
