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AbstractA test array includes row conductors, column conductors, and memory cells located at crossing points of the row and column conductors. The test array can have groups of the row conductors or the column conductors electrically coupled, or ganged together, so that they share common terminals. Other selected row and column conductors can have individual terminals. In this configuration, memory cells located at the intersection of row and column conductors that have individual terminals can have their characteristics measured using a test apparatus. Ganging together groups of row or column conductors means that the test array has fewer terminals for connection to the test apparatus. Therefore, a test apparatus having a limited number of probes for connection to test array terminals can be used to test arrays of various sizes. | InventorAssigneeApplicationNo. 09/983697 filed on 10/25/2001US Classes:365/201, Testing365/214, Particular wiring365/230.03Plural blocks or banksField of Search365/201, Testing365/63, INTERCONNECTION ARRANGEMENTS365/60, Air gap365/69, Crossover365/214, Particular wiring365/230.03Plural blocks or banksExaminersPrimary: Le, Vu A.US Patent References5107459, Stacked bit-line architecture for high density cross-point memory cell arrayIssued on: 04/21/1992 Inventor: Chu, et al.5794175, Low cost, highly parallel memory tester Issued on: 08/11/1998 Inventor: Conner6456525, Short-tolerant resistive cross point array Issued on: 09/24/2002 Inventor: Perner, et al.6552409Techniques for addressing cross-point diode memory arrays Issued on: 04/22/2003 Inventor: Taussig, et al. International ClassesG11C 29/48 (20060101)G11C 29/04 (20060101) G11C 29/18 (20060101) |