Fault tolerant switched communication system
Fault-tolerant multiple processor system with signature voting Patent #: 6128755
ApplicationNo. 09/607677 filed on 06/30/2000
US Classes:714/746, Digital data error correction714/715, Test pattern with comparison714/758, Error correcting code with additional error detection code (e.g., cyclic redundancy character, parity)714/786, Forward error correction by tree code (e.g., convolutional)714/788Burst error
ExaminersPrimary: Moise, Emmanuel L.
International ClassesH03M 13/00 (20060101)
H03M 13/09 (20060101)
AbstractAn apparatus and method for efficiently performing error control coding tasks. An important aspect of the present invention is the provision of an ECC engine that responds to a specialized ECC instruction set having a plurality of instructions, such as a convolutional encoding instruction, a convolutional decoding instruction, and a cyclic redundancy code (CRC) instruction. The ECC engine has a plurality of functional building blocks (e.g., a configurable convolutional encoding functional block, a convolutional configurable decoding functional block, and a configurable cyclic redundancy check (CRC) functional block) that can be programmed or configured. A single instruction provided to the error control coding engine configures one of the functional blocks to execute a error control coding algorithm specified by the instruction. Each instruction also includes a plurality of fields that can be modified by the user. Each modified instruction dynamically re-configures one of the functional building blocks to implement a different ECC algorithm.
Field of SearchDigital data error correction
Error correcting code with additional error detection code (e.g., cyclic redundancy character, parity)
Test pattern with comparison
Double encoding codes (e.g., product, concatenated)
Cross-interleave Reed-Solomon code (CIRC)
Parallel generation of check bits
Forward error correction by tree code (e.g., convolutional)
Random and burst errors