Method and system for providing an electronic system design with enhanced debugging capabilities
November 28, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMultiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device Method and apparatus for debugging reconfigurable emulation systems Method and apparatus for accessing internal integrated circuit signals Method for deciding the feasibility of logic circuit prior to performing logic synthesis Test ready compiler for design for test synthesis Verification system for circuit simulator Method and system for HDL global signal simulation and verification On-chip logic analysis and method for using the same Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits Methods and apparatuses for automatic extraction of finite state machines InventorsAssigneeApplicationNo. 09/724840 filed on 11/28/2000US Classes:716/4, Testing or evaluating714/735, Device response compared to input pattern716/5, Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width)716/6Timing analysis (e.g., delay time, path delay, latch timing)ExaminersPrimary: Smith, MatthewAssistant: Rossoshek, Helen Attorney, Agent or FirmInternational ClassG06T 17/50 (20060101)AbstractTechniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.Other References
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